ITESO - detalle

Publicaciones Recientes

Las publicaciones del dr. Cuauhtémoc Aguilera son las siguientes:

C. R. Aguilera-Galicia, O. Longoria-Gandara, L. Pizano-Escalante, J. Vázquez-Castillo, and M. Salim-Maza, "On-chip implementation of a low-latency bit-accurate reciprocal square root unit," Integration, the VLSI Journal, vol. 63, pp. 9–17, Sep. 2018. (ISSN: 0167-9260; published online: 26 May 2018; DOI: 10.1016/j.vlsi.2018.04.016).
C. R. Aguilera-Galicia, O. Longoria-Gandara, O. A. Guzmán-Ramos, and L. Pizano-Escalante, "IEEE-754 half-precision floating-point low-latency reciprocal square root IP-core," in IEEE Latin American Conf. on Communications, Guadalajara, Mexico, Nov. 2018, vol. 1, pp. 1–6. (ISSN: 2330-989X; p-ISBN: 978-1-5386-6755-2; e-ISBN: 978-1-5386-6754-5; DOI: 10.1109/LATINCOM.2018.8613254).
C. R. Aguilera-Galicia, O. Longoria-Gandara, and L. Pizano-Escalante, "Half-precision floating-point multiplier IP core based on 130 nm CMOS ASIC technology," in IEEE Latin American Conf. on Communications, Guadalajara, Mexico, Nov. 2018, vol. 1, pp. 1–5. (ISSN: 2330-989X; p-ISBN: 978-1-5386-6755-2; e-ISBN: 978-1-5386-6754-5; DOI: 10.1109/LATINCOM.2018.8613231).
C. R. Aguilera-Galicia and O. H. Longoria-Gandara, "Logical synthesis of a basic sequential circuit using RTL Compiler," Internal Report PhDEngScITESO-14-10-R, ITESO, Tlaquepaque, Mexico, Dec. 2014.
C. R. Aguilera-Galicia and O. H. Longoria-Gandara, "Fundamental components for implementing digital VLSI frontend design at ITESO," Internal Report PhDEngScITESO-14-04-R, ITESO, Tlaquepaque, Mexico, Aug. 2014.
C. R. Aguilera-Galicia and O. H. Longoria-Gandara, "Digital integrated circuit design flow using Cadence tools at ITESO," Internal Report PhDEngScITESO-13-04-R, ITESO, Tlaquepaque, Mexico, Dec. 2013.
J. Lanzagorta, M. Bazdresch, C. Aguilera Galicia "An Undergraduate Logic Design Course Based on EDA Tools and Programmable Devices", Primer Workshop Mexicano de Cómputo Reconfigurable y sus Aplicaciones en Educación e Ingeniería, Cancún Quintana Roo, 15 Diciembre 2010 en el marco de ReConFig 2010.