

Dr. J. E. Rayas Sánchez Journal Papers [R27] A. ViverosWacher, J. E. RayasSánchez, and Z. BritoBrito, “Analog gross fault identification in RF circuits using neural models and constrained parameter extraction,” IEEE Trans. Microwave Theory Techn., vol. 67, no. 6, pp. 21432150, Jun. 2019. [R26] I. LomelíIllescas, S. A. SolisBustos, and J. E. RayasSánchez, “A tool for the automatic generation and analysis of regular analog layout modules,” Elsevier Integration  the VLSI Journal, vol. 65, pp. 8187, Mar. 2019. [R25] F. E. RangelPatiño, J. E. RayasSánchez, A. ViverosWacher, J. L. ChávezHurtado, E. A. VegaOchoa, and N. Hakim, “Postsilicon receiver equalization metamodeling by artificial neural networks,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 38, no. 4, pp. 733740, Apr. 2019. [R24] F. E. RangelPatiño, A. ViverosWacher, J. E. RayasSánchez, I. DurónRosales, E. A. VegaOchoa, N. Hakim and E. LópezMiralrio, “A holistic formulation for system margining and jitter tolerance optimization in industrial postsilicon validation,” IEEE Trans. Emerging Topics Computing, (early access; published online: 29 Sep. 2017; regular publication pending). [R23] J. E. RayasSánchez and G. E. Ponchak, “The first IEEE MTTS Latin America microwave conference [Conference Report],” IEEE Microwave Magazine, vol. 18, no. 6, pp. 128131, Sep.Oct. 2017. [R22] F. E. RangelPatiño, J. L. ChávezHurtado, A. ViverosWacher, J. E. RayasSánchez, and N. Hakim, “System margining surrogatebased optimization in postsilicon validation,” IEEE Trans. Microwave Theory Techn., vol. 65, no. 9, pp. 31093115, Sep. 2017. [R21] J. L. ChavezHurtado and J. E. RayasSánchez, “Polynomialbased surrogate modeling of RF and microwave circuits in frequency domain exploiting the multinomial theorem,” IEEE Trans. Microwave Theory Techn., vol. 64, no. 12, pp. 43714381, Dec. 2016. [R20] J. E. RayasSanchez, “Power in simplicity with ASM: tracing the aggressive space mapping algorithm over two decades of development and engineering applications,” IEEE Microwave Magazine, vol. 17, no. 4, pp. 6476, Apr. 2016. [R19] J. C. CervantesGonzález, J. E. RayasSánchez, C. A. López, J. R. CamachoPérez, Z. BritoBrito, and J. L. ChavezHurtado, “Space mapping optimization of handset antennas considering EM effects of mobile phone components and human body,” Int. J. RF and Microwave CAE, vol. 26, no. 2, pp. 121128, Feb. 2016. [R18] J. E. RayasSánchez, J. L. ChavezHurtado, and Z. BritoBrito, “Design optimization of fullwave EM models by loworder lowdimension polynomial surrogate functionals,” Int. J. Numerical Modelling: Electron. Networks, Dev. Fields, vol. 30, no. 34, e2094, MayAug. 2017. (published online: Sep. 2015). [R17] L. M. AguilarLobo, J. R. LooYau, J. E. RayasSánchez, S. OrtegaCisneros, P. Moreno, and J. A. ReynosoHernández, “Application of the NARX neural network as a digital predistortion technique for linearizing microwave power amplifiers,” Microwave and Optical Technology Letters, vol. 57, no. 9, pp. 21372142, Sep. 2015. [R16] J. E. RayasSánchez, D. Pasquet, B. Szendrenyi, and M. S. Gupta, “MTTS Mexico trip: addressing the RF and microwave community in Mexico,” IEEE Microwave Magazine, vol. 16, pp. 104107, Aug. 2015. [R15] R. Murphy, R. Torres, J. E. RayasSánchez, A. Reynoso, M. MayaSánchez, A. Henze, A. Zozaya, P. del Pino, J. Pena, G. RafaelValdivia, “R&D in Latin America: RF and microwave research in Latin America,” IEEE Microwave Magazine, vol. 15, pp. 97103, May 2014. [R14] V. GutiérrezAyala and J. E. RayasSánchez, “Neural input space mapping optimization based on nonlinear twolayer perceptrons with optimized nonlinearity,” Int. J. RF and Microwave CAE, vol. 20, pp. 512526, Sep. 2010. [R13] Q. S. Cheng, J. W. Bandler and J. E. RayasSánchez, “Tuningaided implicit space mapping,” Int. J. RF and Microwave CAE, vol. 18, pp. 445453, Sep. 2008. [R12] J. E. RayasSánchez and V. GutiérrezAyala, “EMbased Monte Carlo analysis and yield prediction of microwave circuits using linearinput neuraloutput space mapping,” IEEE Trans. Microwave Theory Tech., vol. 54, pp. 45284537, Dec. 2006. [R11] J. E. RayasSánchez, F. LaraRojo and E. MartínezGuerrero, “A linear inverse space mapping (LISM) algorithm to design linear and nonlinear RF and microwave circuits,” IEEE Trans. Microwave Theory Tech., vol. 53, pp. 960968, Mar. 2005. [R10] J. E. RayasSánchez, “A frequencydomain approach to interconnect crosstalk simulation and minimization,” Elsevier Microelectronics Reliability, vol. 44, pp. 673681, Apr. 2004. [R9] J. E. RayasSánchez, “EMbased optimization of microwave circuits using artificial neural networks: the state of the art,” IEEE Trans. Microwave Theory Tech., vol. 52, pp. 420435, Jan. 2004. [R8] J. W. Bandler, M. A. Ismail, J. E. RayasSánchez and Q. J. Zhang, “Neural inverse space mapping (NISM) for EMbased microwave design,” Int. J. RF and Microwave CAE, vol. 13, pp. 136147, Mar. 2003. [R7] J. W. Bandler, M. A. Ismail and J. E. RayasSánchez, “Expanded space mapping EM based design framework exploiting preassigned parameters,” IEEE Trans. Circuits Sys. I, vol. 49, pp. 18331838, Dec. 2002. [R6] J. W. Bandler, J. E. RayasSánchez and Q. J. Zhang, “Yielddriven electromagnetic optimization via space mappingbased neuromodels,” Int. J. RF and Microwave CAE, vol. 12, pp. 7989, Jan. 2002. [R5] J. W. Bandler, M. A. Ismail and J. E. RayasSánchez, “Broadband physicsbased modeling of microwave passive devices through frequency mapping,” Int. J. RF and Microwave CAE, vol. 11, pp. 156170, May 2001. [R4] J. W. Bandler, N. Georgieva, M. A. Ismail, J. E. RayasSánchez and Q. J. Zhang, “A generalized space mapping tableau approach to device modeling,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 6779, Jan. 2001. [R3] M. H. Bakr, J. W. Bandler, K. Madsen, J. E. RayasSánchez and J. Søndergaard, “Space mapping optimization of microwave circuits exploiting surrogate models,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 22972306, Dec. 2000. [R2] M. H. Bakr, J. W. Bandler, M. A. Ismail, J. E. RayasSánchez and Q. J. Zhang, “Neural space mapping optimization for EMbased design,” IEEE Trans. Microwave Theory Tech., vol. 48, pp. 23072315, Dec. 2000. [R1] J. W. Bandler, M. A. Ismail, J. E. RayasSánchez and Q. J. Zhang, “Neuromodeling of microwave circuits exploiting space mapping technology,” IEEE Trans. Microwave Theory Tech., vol. 47, pp. 24172427, Dec. 1999. Book Chapters [BC3] J. E. RayasSánchez, “Artificial neural networks and space mapping for EMbased modeling and design of microwave circuits,” in SurrogateBased Modeling and Optimization: Applications in Engineering, S. Koziel and L. Leifsson, Ed., New York, NY: Springer, 2013, ch. 7, pp. 147169. [BC2] J. E. RayasSánchez, “Neural space mapping methods for EMbased yield estimation,” in SimulationDriven Design Optimization and Modeling for Microwave Engineering, S. Koziel, XS Yang, and Q. J. Zhang, Ed., London, England: Imperial College Press, 2013, ch. 11, pp. 271310. [BC1] J. E. RayasSánchez, “Electromagneticsbased design using artificial neural networks,” in Special Topics of EMC at Chip and System Levels, D. Lupi, Ed., Buenos Aires, Argentina: Dunken, Programa CYTED (Programa Iberoamericano de Ciencia y Tecnología para el Desarrollo), 2006, ch. 3, pp. 75129 . Conference Papers [C102] B. MercadoCasillas and J. E. RayasSánchez, “Towards signalpower integrity analysis by efficient power delivery network lumped models obtained from parameter extraction,” in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2019), Montreal, Canada, Oct. 2019, pp. 13. [C101] J. E. RayasSánchez and Z. BritoBrito, “Applications of Broydenbased input space mapping to modeling and design optimization in hightech companies in Mexico,” in European Microwave Conf. (EuMC2019), Paris, France, Oct. 2019, pp. 272275. [C100] R. J. SánchezMesa, D. M. CortésHernández, J. E. RayasSánchez, Z. BritoBrito, and L. delaMoraHernández, “EM parametric study of length matching elements exploiting an ANSYS HFSS MatlabPython driver,” in IEEE MTTS Latin America Microwave Conf. (LAMC2018), Arequipa, Peru, Dec. 2018, pp. 13. [C99] F. LealRomo, J. L. ChávezHurtado, and J. E. RayasSánchez, “Selecting surrogatebased modeling techniques for power integrity analysis,” in IEEE MTTS Latin America Microwave Conf. (LAMC2018), Arequipa, Peru, Dec. 2018, pp. 13. [C98] R. J. SánchezMesa, D. M. CortésHernández, B. GálvezSahagún, J. E. RayasSánchez, and Z. BritoBrito, “A novel highperformance length matching element for highspeed interconnect differential channels,” in IEEE MTTS Latin America Microwave Conf. (LAMC2018), Arequipa, Peru, Dec. 2018, pp. 13. [C97] F. E. RangelPatiño, J. E. RayasSánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for highspeed links in industrial computer platforms postsilicon validation,” in Int. Test Conf. (ITC2018), Phoenix, AZ, Oct. 2018, pp. 110. [C96] J. E. RayasSánchez, F. E. RangelPatiño, A. ViverosWacher, J. L. ChávezHurtado, J. R. delRey, F. LealRomo, and Z. BritoBrito, “Industryoriented research projects on computeraided design of highfrequency circuits and systems at ITESO Mexico,” in European Microwave Conf. (EuMC2018), Madrid, Spain, Sep. 2018, pp. 588591. [C95] A. ViverosWacher and J. E. RayasSánchez, “Analog fault identification in RF circuits using artificial neural networks and constrained parameter extraction,” in IEEE MTTS Int. Conf. Num. EM Mutiphysics Modeling Opt. (NEMO2018), Reykjavik, Iceland, Aug. 2018, pp. 13. [C94] F. E. RangelPatiño, J. E. RayasSánchez, A. ViverosWacher, E. A. VegaOchoa, and N. Hakim, “Highspeed links receiver optimization in postsilicon validation exploiting Broydenbased input space mapping,” in IEEE MTTS Int. Conf. Num. EM Mutiphysics Modeling Opt. (NEMO2018), Reykjavik, Iceland, Aug. 2018, pp. 13. [C93] F. LealRomo, J. L. SilvaPerales, C. LópezLimón, and J. E. RayasSánchez, “Optimizing phase settings of highfrequency voltage regulators for power delivery applications,” in IEEE Workshop on Signal and Power Integrity (SPI2018), Brest France, May 2018, pp. 14 . [C92] F. E. RangelPatiño, J. E. RayasSánchez, E. A. VegaOchoa, and N. Hakim, “Direct optimization of a PCI Express link equalization in industrial postsilicon validation,” in IEEE Latin American Test Symp. (LATS 2018), Sao Paulo, Brazil, Mar. 2018, poster. [C91] F. E. RangelPatiño, J. E. RayasSánchez, E. A. VegaOchoa, and N. Hakim, “Direct optimization of a PCI Express link equalization in industrial postsilicon validation,” in IEEE Latin American Test Symp. (LATS 2018), Sao Paulo, Brazil, Mar. 2018, pp. 16. [C90] A. ViverosWacher, R. BacaBaylón, F. E. RangelPatiño, M. A. DávalosSantana, E. A. VegaOchoa, and J. E. RayasSánchez, “Jitter tolerance acceleration using the golden section optimization technique,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2018), Puerto Vallarta, Mexico, Feb. 2018, pp. 14. [C89] F. LealRomo, M. CabreraGómez, J. E. RayasSánchez, and D. M. GarcíaMora, “Design optimization of a planar spiral inductor using space mapping,” in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2017), San Jose, CA, Oct. 2017, poster. [C88] F. LealRomo, M. CabreraGómez, J. E. RayasSánchez, and D. M. GarcíaMora, “Design optimization of a planar spiral inductor using space mapping,” in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2017), San Jose, CA, Oct. 2017, pp. 13. [C87] F. RangelPatino, J. L. ChávezHurtado, A. ViverosWacher, J. E. RayasSánchez, and N. Hakim, “Eye diagram system margining surrogatebased optimization in a server silicon validation platform,” in European Microwave Conf. (EuMC2017), Nuremberg, Germany, Oct. 2017, pp. 540543. [C86] J. E. RayasSánchez and Z. BritoBrito, “Academic and industrial research activities on RF and microwaves in Latin America: an overview,” in European Microwave Conf. (EuMC2017), Nuremberg, Germany, Oct. 2017, pp. 536539. [C85] J. E. RayasSánchez, “A historical account and technical reassessment of the Broydenbased input space mapping optimization algorithm,” in IEEE MTTS Int. Microwave Symp. Dig., Honolulu, HI, Jun. 2017, pp. 13. [C84] A. CorresMatamoros, E. MartínezGuerrero, and J. E. RayasSánchez, “Design and validation of a portable radiofrequency diathermy prototype,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS2017), Cozumel, Mexico, Jun. 2017, poster. [C83] A. CorresMatamoros, E. MartínezGuerrero, and J. E. RayasSánchez, “Design and validation of a portable radiofrequency diathermy prototype,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS2017), Cozumel, Mexico, Jun. 2017, pp. 9396. [C82] I. DuronRosales, F. RangelPatino, J. E. RayasSánchez, J. L. ChávezHurtado, and N. Hakim, “Reconfigurable FIR filter coefficient optimization in postsilicon validation to improve eye diagram for optical interconnects,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS2017), Cozumel, Mexico, Jun. 2017, pp. 8588. [C81] A. CorresMatamoros, E. MartínezGuerrero, and J. E. RayasSánchez, “A programmable CMOS voltage controlled ring oscillator for radiofrequency diathermy onchip circuit,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS2017), Cozumel, Mexico, Jun. 2017, pp. 6568. [C80] I. LomelíIllescas, S. A. SolisBustos, and J. E. RayasSánchez, “Analysis of the implications of stacked devices in nanoscale technologies for analog applications,” in IEEE Latin American Test Symp. (LATS2017), Bogota, Colombia, Mar. 2017, pp. 14. [C79] F. LealRomo, J. E. RayasSánchez, and J. He, “Design of experiments implementation towards optimization of power distribution networks,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2017), Bariloche, Argentina, Feb. 2017, pp. 14. [C78] A. ViverosWacher and J. E. RayasSánchez, “Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links,” in IEEE MTTS Latin America Microwave Conf. (LAMC2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 13. [C77] F. RangelPatino, A. ViverosWacher, J. E. RayasSánchez, E. A. VegaOchoa, I. DuronRosales, and N. Hakim, “A holistic methodology for system margining and jitter tolerance optimization in postsilicon validation,” in IEEE MTTS Latin America Microwave Conf. (LAMC2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 14. [C76] J. R. delRey, Z. BritoBrito, J. E. RayasSánchez, and N. Izquierdo, “Temperature effects in automotivegrade high speed interconnects,” in IEEE MTTS Latin America Microwave Conf. (LAMC2016), Puerto Vallarta, Mexico, Dec. 2016, poster. [C75] J. R. delRey, Z. BritoBrito, J. E. RayasSánchez, and N. Izquierdo, “Temperature effects in automotivegrade high speed interconnects,” in IEEE MTTS Latin America Microwave Conf. (LAMC2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 14. [C74] J. L. ChávezHurtado, J. E. RayasSánchez, and Z. BritoBrito, “Multiphysics polynomialbased surrogate modeling of microwave structures in frequency domain,” in IEEE MTTS Latin America Microwave Conf. (LAMC2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 13. [C73] I. LomelíIllescas, S. A. SolisBustos, V. H. MartínezSánchez and J. E. RayasSánchez, “Synthesis tool for automatic layout generation of analog structures,” in IEEE ANDESCON Proc., Arequipa, Peru, Oct. 2016, pp. 14. [C72] J. L. ChávezHurtado and J. E. RayasSánchez, “Polynomialbased surrogate modeling of microwave structures in frequency domain exploiting the multinomial theorem,” in IEEE MTTS Int. Microwave Symp. Dig., San Francisco, CA, May 2016, pp. 13. [C71] J. E. RayasSánchez, J. L. ChávezHurtado, and Z. BritoBrito, “Enhanced formulation for polynomialbased surrogate modeling of microwave structures in frequency domain,” in IEEE MTTS Int. Conf. Num. EM Mutiphysics Modeling Opt. RF, Microw., Terahertz App. (NEMO2015), Ottawa, ON, Aug. 2015, pp. 13. [C70] Z. BritoBrito, J. E. RayasSánchez, and J. L. ChávezHurtado, “Enhanced procedure to setup the simulation bounding box and the meshing scheme of a 3D finite element EM simulator for planar microwave structures,” in IEEE MTTS Int. Microwave Symp. Dig., Phoenix, AZ, May. 2015, pp. 13. [C69] J. Rafael delRey, Z. BritoBrito, and J. E. RayasSánchez, “Impedance matching analysis and EMC validation of a lowcost PCB differential interconnect,” in IEEE Latin American Test Symp. (LATS2015), Puerto Vallarta, Mexico, Mar. 2015, pp. 15. [C68] J. L. ChávezHurtado, J. E. RayasSánchez, and Z. BritoBrito, “Reliable fullwave EM simulation of a singlelayer SIW interconnect with transitions to microstrip lines,” in COMSOL Conf., Boston, MA, Oct. 2014, pp. 15. [C67] L. M. AguilarLobo, A. GarciaOsorio, J. R. LooYau, S. OrtegaCisneros, P. Moreno, J. E. RayasSánchez, and J. A. ReynosoHernández, “A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers,” in IEEE Int. Midwest Symp. Circuits Syst., College Station, TX, Aug. 2014, poster. [C66] L. M. AguilarLobo, A. GarciaOsorio, J. R. LooYau, S. OrtegaCisneros, P. Moreno, J. E. RayasSánchez, and J. A. ReynosoHernández, “A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers,” in IEEE Int. Midwest Symp. Circuits Syst., College Station, TX, Aug. 2014, pp. 717720. [C65] J. E. RayasSánchez and Z. BritoBrito, “Research activities on computeraided modeling, design and optimization of RF and microwave circuits at ITESO Mexico” in IEEE MTTS Int. Microwave Symp. Dig., Tampa, FL, Jun. 2014, pp. 13. [C64] Z. BritoBrito, J. E. RayasSánchez, J. C. CervantesGonzález, and C. A. López, “Impact of 3D EM model configuration on the direct optimization of microstrip structures,” in COMSOL Conf., Boston, MA, Oct. 2013, pp. 15. [C63] J. C. CervantesGonzález, C. A. López, J. E. RayasSánchez, Z. BritoBrito and G. HernándezSosa, “Returnloss minimization of package interconnects through input space mapping using FEMbased models,” in Proc. SBMO/IEEE MTTS Int. Microwave Optoelectronics Conf. (IMOC2013), Rio de Janeiro, Brazil, Aug. 2013, pp. 14. [C62] J. E. RayasSánchez, Z. BritoBrito, J. C. CervantesGonzález, and C. A. López, “Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of highfrequency planar structures,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2012), Cuzco, Peru, Feb. 2013, pp. 14. [C61] D. BecerraPérez and J. E. RayasSánchez, “Optimization of the stubalternated and serpentine microstrip structures to minimize farend crosstalk,” in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2012), Tempe, AZ, Oct. 2012, pp. 109112. [C60] J. E. RayasSánchez, J. AguilarTorrentera, Z. BritoBrito, J. C. CervantesGonzález, and C. A. López, “EM simulation of a lowpass filter based on a microstrip defected ground structure,” in COMSOL Conf., Boston, MA, Oct. 2012, pp. 16. [C59] J. E. RayasSánchez and E. EstradaArámbula, “EMbased design optimization of microstrip lines traversing a rectangular gap in the reference plane,” in Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012, pp. 197200. [C58] J. E. RayasSánchez and Q. J. Zhang, “On knowledgebased neural networks and neurospace mapping,” in IEEE MTTS Int. Microwave Symp. Dig., Montreal, Canada, Jun. 2012, pp. 13. [C57] F. LealRomo, R. MoreyraGonzález, and J. E. RayasSánchez, “HFSS automated driver based on nonGUI scripting for EMbased design of highfrequency circuits,” in IEEE Latin American Symposium on Circuits and Systems (LASCAS 2012), Playa del Carmen, Mexico, Feb. 2012, pp. 14. [C56] J. E. RayasSánchez and N. VargasChávez, “A linear regression inverse space mapping algorithm for EMbased design optimization of microwave circuits,” in IEEE MTTS Int. Microwave Symp. Dig., Baltimore, MD, Jun. 2011, pp. 14. [C55] J. E. RayasSánchez, “EMbased design optimization of RF and microwave circuits using functional surrogate models,” in IEEE MTTS Int. Microwave Symp. Workshop Notes and Short Courses, Baltimore, MD, Jun. 2011. [C54] D. BecerraPérez and J. E. RayasSánchez, “Driving Sonnet through a Pythonbased interface,” in Int. Review of Progress in Applied Computational Electromagnetics (ACES 2011), Williamsburg, VA, Mar. 2011, pp. 412417. [C53] J. E. RayasSánchez and N. VargasChávez, “Design optimization of microstrip lines with via fences through surrogate modeling based on polynomial functional interpolants,” in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2010), Austin, TX, Oct. 2010, pp. 125128. [C52] J. E. RayasSánchez and D. E. CorderoBaltazar, “Impact of base points distributions on the polynomial surrogate modeling of a substrate integrated waveguide with microstrip transitions,” in Electronics, Robotics and Automotive Mechanics Conf. (CERMA 2010), Cuernavaca, Mexico, Sep. 2010, pp. 705710 . [C51] J. E. RayasSánchez, J. AguilarTorrentera and J. A. JassoUrzúa, “Surrogate modeling of microwave circuits using polynomial functional interpolants,” in IEEE MTTS Int. Microwave Symp. Dig., Anaheim, CA, May 2010, pp. 197200. [C50] S. Ogurtsov, S. Koziel and J. E. RayasSánchez, “Design optimization of a broadband microstriptoSIW transition using surrogate modeling and adaptive design specifications,” in Int. Review of Progress in Applied Computational Electromagnetics (ACES2010), Tampere, Finland, Apr. 2010, pp. 878883. [C49] L. N. PérezAcosta and J. E. RayasSánchez, “Design of a CMOS second order bandpass continuous time filter using numerical optimization,” in IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS 2009), Cancun, Mexico, Aug. 2009, pp. 204207. [C48] J. L. ChávezHurtado, E. MartínezGuerrero and J. E. RayasSánchez, “Design of reusable CMOS OTAs using CAD tools,” in IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS 2009), Cancun, Mexico, Aug. 2009, pp. 228231. [C47] J. E. RayasSánchez, “Neural Space Mapping Approaches to EMbased Statistical Analysis,” in IEEE MTTS Int. Microwave Symp. Workshop Notes and Short Courses, Boston, MA, Jun. 2009. [C46] J. E. RayasSánchez and J. A. JassoUrzúa, “EMbased optimization of a single layer SIW with microstrip transitions using linear output space mapping,” in IEEE MTTS Int. Microwave Symp. Dig., Boston, MA, Jun. 2009, pp. 525528. [C45] J. E. RayasSánchez, “An improved EMbased design procedure for singlelayer substrate integrated waveguide interconnects with microstrip transitions,” in IEEE MTTS Int. Microwave Workshop Series in Region 9 (IMWS2009R9) on Signal Integrity and HighSpeed Interconnects, Guadalajara, Mexico, Feb. 2009, pp. 2730. [C44] J. E. RayasSánchez and V. GutiérrezAyala, “A general EMbased design procedure for singlelayer substrate integrated waveguide interconnects with microstrip transitions,” in IEEE MTTS Int. Microwave Symp. Dig., Atlanta, GA, Jun. 2008, pp. 983986. [C43] Q. J. Zhang and J. E. RayasSánchez, “Fast parametric models for EM design using neural networks and space mapping,” in IEEE MTTS Int. Microwave Symp. Workshop Notes and Short Courses, Atlanta, GA, Jun. 2008. [C42] L. N. PérezAcosta and J. E. RayasSánchez, “A numerical optimization procedure to obtain SPICE MOSFET model level 1 parameters from model level 49,” in XIV International Workshop Iberchip (IWS2008), Puebla, Mexico, Feb. 2008, ISBN13 9789687938035. [C41] J. E. RayasSánchez and V. GutiérrezAyala, “EMbased parametric optimization of a transition from microstrip to substrate integrated waveguide interconnect,” in 9^{th} IEEE LatinAmerican Test Workshop (LATW2008), Puebla, Mexico, Feb. 2008, pp. 145150. [C40] L. J. Roglá, J. E. RayasSánchez, V. E. Boria and J. Carbonell, “EMbased space mapping optimization of lefthanded coplanar waveguide filters with split ring resonators,” in IEEE MTTS Int. Microwave Symp. Dig., Honolulu, HI, Jun. 2007, pp. 111114. [C39] L. N. PérezAcosta, J. E. RayasSánchez and E. MartínezGuerrero, “Optimal design of a classical CMOS OTAMiller using numerical methods and SPICE simulations,” in XIII International Workshop Iberchip (IWS2007), Lima, Peru, Mar. 2007, pp. 387390. [C38] V. GutiérrezAyala and J. E. RayasSánchez, “Highfrequency circuit design using a neural spacemapping algorithm based on a twolayer perceptron with optimized nonlinearity,” in Int. Conf. on Electronic Design Proc. (ICED2006), Veracruz, Mexico, Nov. 2006, pp. 9095. [C37] J. E. RayasSánchez, “Linearinput and neuraloutput space mapping for highly accurate statistical analysis and yield prediction,” in Second Int. Workshop on Surrogate Modeling and Space Mapping for Engineering Optimization (SMSMEO06), Lyngby, Denmark, Nov. 2006. [C36] J. E. RayasSánchez and V. GutiérrezAyala, “EMbased statistical analysis and yield estimation using linearinput and neuraloutput space mapping,” in IEEE MTTS Int. Microwave Symp. Dig., San Francisco, CA, June 2006, pp. 15971600. [C35] V. GutiérrezAyala and J. E. RayasSánchez, “Diseño de circuitos de alta frecuencia usando mapeo espacial neural con nolinealidad regulada,” in XII International Workshop Iberchip (IWS2006), San José, Costa Rica, March 2006, pp. 150153. [C34] Q. J. Zhang, L. Zhang and J. E. RayasSánchez, “Automated modeling and neuro space mapping for microwave design,” in IEEE MTTS Int. Microwave Symp. Workshop Notes and Short Courses, Long Beach, CA, June 2005. [C33] J. E. RayasSánchez, “Electromagneticsbased design through inverse space mapping techniques,” in IEEE MTTS Int. Microwave Symp. Workshop Notes and Short Courses, Fort Worth, TX, June 2004. [C32] J. E. RayasSánchez, F. LaraRojo and E. MartínezGuerrero, “A linear inverse space mapping algorithm for microwave design in the frequency and transient domains,” in IEEE MTTS Int. Microwave Symp. Dig., Fort Worth, TX, poster, June 2004. [C31] J. E. RayasSánchez, F. LaraRojo and E. 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