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Research Group on Computer-Aided Engineering of Circuits and Systems (CAECAS)
A. E. Moreno-Mojica, Decoupling Capacitors Optimization Methodologies for Power Delivery Networks in Computer Platforms, PhD Thesis, Dept. of Electronics, Systems, and Informatics, ITESO, Tlaquepaque, Mexico, 2022. [Supervisor: J. E. Rayas-Sánchez; Pages: xxix, 135; Date: Nov. 30, 2022]. B. Mercado-Casillas, Analysis and Design of Power Delivery Networks Exploiting Simulation Tools and Numerical Optimization Techniques, Master’s Thesis, Dept. of Electronics, Systems, and Informatics, ITESO, Tlaquepaque, Mexico, 2021. [Supervisor: J. E. Rayas-Sánchez; Pages: ix, 112; Date: Feb. 12, 2021].
A. Viveros-Wacher, Machine Learning Techniques and Optimization Approaches for Analog Validation and Testing, PhD Thesis, Dept. of Electronics, Systems, and Informatics, ITESO, Tlaquepaque, Mexico, 2020. [Supervisor: J. E. Rayas-Sánchez; Pages: xxxii, 141; Date: Dec. 10, 2020].
J. R. del-Rey-Acuña,
Development of Cost-Effective High-Speed Printed
Circuit Board Interconnects for Mass Production towards the Connected Car,
PhD Thesis, Dept. of Electronics, Systems, and Informatics, ITESO, Tlaquepaque,
Mexico, 2018. [Supervisor: Z. Brito-Brito; Co-Supervisor: J. E. Rayas-Sánchez;
Pages: xxix, 164; Date: July 12, 2018].
F. E. Rangel-Patiño,
Transmitter and Receiver Equalizers Optimization
Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon
Validation, PhD Thesis, Dept. of Electronics, Systems, and
Informatics, ITESO, Tlaquepaque, Mexico, 2018. [Supervisor: J. E. Rayas-Sánchez;
Co-Supervisor: N. Hakim; Pages: xxx, 168; Date: July 10, 2018].
J. L.
Chávez-Hurtado,
Multiphysics Design of
High Frequency Circuits by Polynomial Surrogate Modeling exploiting the
Multinomial Theorem, PhD Thesis, Dept. of Electronics, Systems,
and Informatics, ITESO, Tlaquepaque, Mexico, 2017.
[Supervisor: J. E. Rayas-Sánchez; Co-Supervisor: Z. Brito-Brito; Pages: xxvi,
90; Date: Dec. 6, 2017].
J. R.
Alejos-Jiménez,
High-Frequency Electronic
Design Optimization using Simulated Annealing, Master’s Thesis,
Dept. of Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2017.
[Supervisor: J. E. Rayas-Sánchez; Pages: viii, 52; Date: Nov. 2017].
J. A.
Robledo-Mariscal,
Frequency Domain
Optimization Based Methodology to Accelerate High Speed Digital Interconnect
Design, Master’s Thesis, Dept. of Electronics, Systems and
Informatics, ITESO, Tlaquepaque, Mexico, 2017.
[Supervisor: J. E. Rayas-Sánchez; Pages: viii,
68; Date: Mar. 2017].
J.
García-Bedoy-Torres,
Improving Harmonic
Balance Performance via Parallelization, Master’s Thesis, Dept.
of Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2016.
[Supervisor: J. E. Rayas-Sánchez; Pages: viii, 74; Date: June 2016].
E. R.
Villa-Loustaunau, Parameter Extraction Methodology for Composite Right/Left-Handed
Transmission Lines using Quasi-static Models, Master’s Thesis, Dept. of
Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2014.
[Supervisor: J. E. Rayas-Sánchez; Pages: ix, 142; Date: Sept. 2014].
C. A.
Jacinto-Navarro, EM-based Modeling of Typical Interconnect Discontinuities using
Linear Input Space Mapping, Master’s Thesis, Dept. of Electronics,
Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2013.
[Supervisor: J. E. Rayas-Sánchez; Pages: ix, 102; Date:
Sept. 2013].
E.
Estrada-Arámbula, Minimizing Negative Effects on Microstrip Lines due to Discontinuities
in the Reference Plane, Master’s Thesis, Dept. of Electronics, Systems and
Informatics, ITESO, Tlaquepaque, Mexico, 2013.
[Supervisor: J. E. Rayas-Sánchez; Pages: viii, 85; Date: June 2013].
D.
Becerra-Pérez, Far-end Crosstalk Reduction on Microstrip Lines through the Optimization
of Alternative Microstrip Structures, Master’s Thesis, Dept. of Electronics,
Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2012.
[Supervisor: J. E. Rayas-Sánchez; Pages:
ix, 106; Date: Sept. 2012]. N. Vargas-Chávez,
Configuración de Herramientas de CAD para la Simulación EM de Estructuras de
Interconexión y su Aplicación en Optimización Avanzada, Master’s Thesis,
Dept. of Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2011.
[Supervisor: J. E. Rayas-Sánchez; Pages: viii,
128; Date: Nov. 2011].
D. E.
Cordero-Baltazar, Electromagnetics-based Optimization of Substrate Integrated Waveguide
Interconnects, Master’s Thesis, Dept. of Electronics, Systems and
Informatics, ITESO, Tlaquepaque, Mexico, 2011.
[Supervisor: J. E. Rayas-Sánchez; Pages: ix, 151; Date: Sept. 2011].
L. N.
Pérez-Acosta, CMOS Integrated Circuit Design Exploiting Numerical Optimization Methods,
Master’s Thesis, Dept. of Electronics, Systems and Informatics, ITESO,
Tlaquepaque, Mexico, 2009.
[Supervisor: J. E. Rayas-Sánchez; Pages: vii,
114; Date: Sept. 2009].
J. A.
Jasso-Urzúa, Use of CST Microwave Studio and its Interface with Matlab for
Optimization and Space Mapping Applications, Master’s Thesis, Dept. of
Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2009.
[Supervisor: J. E. Rayas-Sánchez; Pages:
ix, 174; Date: Sept. 2009]. M. Trejo-Lam,
Neuromodelado de Dispositivos Electrónicos
utilizando Perceptrones de Tres Capas, Master’s Thesis, Dept. of
Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2007.
[Supervisor: J. E. Rayas-Sánchez; Pages:
viii, 96; Date: Nov. 2007]. J. F. Enríquez-de-la-O,
Diseño de Circuitos Analógicos mediante
Optimización Numérica con Formulación Minimax, Master’s Thesis, Dept. of
Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2006.
[Supervisor: J. E. Rayas-Sánchez; Pages:
ix, 143; Date: July 2006]. V. Gutiérrez-Ayala, Diseño de Circuitos de Alta Frecuencia usando Mapeo Espacial Neural con No Linealidad Regulada, Master’s Thesis, Dept. of Electronics, Systems and Informatics, ITESO, Tlaquepaque, Mexico, 2006. [Supervisor: J. E. Rayas-Sánchez; Pages: viii, 89; Date: Mar. 2006].
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