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Research Group on Computer-Aided Engineering of Circuits and Systems (CAECAS)
[246] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Optimizing the full mixed-mode performance of a differential microstrip interconnect with a right-angle bend and two symmetrical bumps,” Internal Report PhDEngScITESO-24-10-R (CAECAS-24-01-R), ITESO, Tlaquepaque, Mexico, May 2024.
[245] R. Loera-Díaz and J. E. Rayas-Sánchez, “Parameter extraction graphical study using Kullback-Leibler formulations,” Internal Report PhDEngScITESO-23-13-R (CAECAS-23-04-R), ITESO, Tlaquepaque, Mexico, Dec. 2023.
[244] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Minimizing differential to common mode conversion caused by a right-angle bend in a differential microstrip interconnect by using two symmetric length match bumps,” Internal Report PhDEngScITESO-23-10-R (CAECAS-23-03-R), ITESO, Tlaquepaque, Mexico, Dec. 2023.
[243] R. Loera-Díaz and J. E. Rayas-Sánchez, “Comparison of ADS circuital models for a microstrip low-pass filter,” Internal Report PhDEngScITESO-23-05-R (CAECAS-23-02-R), ITESO, Tlaquepaque, Mexico, Aug. 2023.
[242] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Minimizing differential to common mode conversion caused by a right-angle bend in a differential microstrip interconnect by using a length match bump,” Internal Report PhDEngScITESO-23-01-R (CAECAS-23-01-R), ITESO, Tlaquepaque, Mexico, Feb. 2023.
[241] R. Loera-Díaz and J. E. Rayas-Sánchez, “Validating electromagnetic models implemented in ADS Momentum for several filters in microstrip technology,” Internal Report PhDEngScITESO-22-19-R (CAECAS-22-07-R), ITESO, Tlaquepaque, Mexico, Nov. 2022.
[240] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Confirming symmetry on mixed mode S-parameters for reciprocal networks,” Internal Report PhDEngScITESO-22-18-R (CAECAS-22-06-R), ITESO, Tlaquepaque, Mexico, Nov. 2022.
[239] R. J. Sánchez-Mesa and J. E. Rayas-Sánchez, “Comparing several techniques to reduce skew in serial high-speed differential interconnects within a pin field region,” Internal Report PhDEngScITESO-22-12-R (CAECAS-22-05-R), ITESO, Tlaquepaque, Mexico, Sep. 2022.
[238] A. E. Moreno-Mojica and J. E. Rayas-Sánchez, “Developing a physics-based lumped circuit model for lossless parallel plates,” Internal Report PhDEngScITESO-22-06-R (CAECAS-22-04-R), ITESO, Tlaquepaque, Mexico, Jul. 2022.
[237] A. E. Moreno-Mojica and J. E. Rayas-Sánchez, “Full-wave EM simulations of a parallel plane power delivery network,” Internal Report PhDEngScITESO-22-05-R (CAECAS-22-03-R), ITESO, Tlaquepaque, Mexico, Jul. 2022.
[236] R. J. Sánchez-Mesa and J. E. Rayas-Sánchez, “Comparison of 3D EM-based models of an MLCC mounted on a microstrip support structure,” Internal Report PhDEngScITESO-22-04-R (CAECAS-22-02-R), ITESO, Tlaquepaque, Mexico, May 2022.
[235] R. J. Sánchez-Mesa, J. E. Rayas-Sánchez, and Z. Brito-Brito, “Voids under pads used for multilayer ceramic capacitors in single-ended channels,” Internal Report PhDEngScITESO-22-02-R (CAECAS-22-01-R), ITESO, Tlaquepaque, Mexico, Mar. 2022.
[234] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Minimizing mode conversion caused by a right-angle bend in a differential microstrip interconnect by using a length match bump,” Internal Report PhDEngScITESO-21-17-R (CAECAS-21-09-R), ITESO, Tlaquepaque, Mexico, Nov. 2021.
[233] A. E. Moreno-Mojica and J. E. Rayas-Sánchez, “Optimizing the performance yield of a PDN subject to large variability in decoupling capacitor tolerances,” Internal Report PhDEngScITESO-21-16-R (CAECAS-21-08-R),
ITESO, Tlaquepaque, Mexico, Nov. 2021.
[232] A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and Felipe J. Leal-Romo, “Evaluating the impact of decoupling capacitors variability on the performance of a power delivery network,” Internal Report PhDEngScITESO-21-07-R (CAECAS-21-07-R),
ITESO, Tlaquepaque, Mexico, Sep. 2021.
[231] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “An introduction to mode conversion in high-speed differential interconnects,” Internal Report PhDEngScITESO-21-06-R (CAECAS-21-06-R),
ITESO, Tlaquepaque, Mexico, Sep. 2021.
[230] A. E. Moreno-Mojica and J. E. Rayas-Sánchez, “Time- and memory-efficient yield analysis in Keysight ADS through Matlab,” Internal Report PhDEngScITESO-21-04-R (CAECAS-21-05-R),
ITESO, Tlaquepaque, Mexico, Aug. 2021.
[229] J. E. Rayas-Sánchez, “Configuring Keysight Momentum for reliable
full-wave EM simulation of microstrip lines,” Internal Report CAECAS-21-04-R,
ITESO, Tlaquepaque, Mexico, Jul. 2021. [228] R. J. Sánchez-Mesa, J. E. Rayas-Sánchez, and Z. Brito-Brito, “An
overview on multilayer ceramic capacitors,” Internal Report
PhDEngScITESO-21-03-R (CAECAS-21-03-R), ITESO, Tlaquepaque, Mexico, Apr.
2021. [227] A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and F. J. Leal-Romo, “An
enhanced formulation for optimizing a buck voltage regulator and the number of
decoupling capacitors for a PDN application,” Internal Report
PhDEngScITESO-21-02-R (CAECAS-21-02-R), ITESO, Tlaquepaque, Mexico, Apr.
2021. [226] A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and F. J. Leal-Romo, “Optimizing a buck voltage regulator and the number of decoupling capacitors for a PDN application,” Internal Report PhDEngScITESO-21-01-R (CAECAS-21-01-R), ITESO, Tlaquepaque, Mexico, Feb. 2021. [225] J. Dávalos-Guzmán, Z. Brito-Brito, J. E. Rayas-Sánchez, and J. L.
Chávez-Hurtado, “Kriging-based surrogate optimization of a microstrip low-pass
filter in the frequency domain,” Internal Report PhDEngScITESO-20-22-R
(CAECAS-20-10-R), ITESO, Tlaquepaque, Mexico, Dec. 2020. [224] R. Loera-Díaz, J. E. Rayas-Sánchez, and Z. Brito-Brito, “A comparative study of several topologies for band-pass and band-stop filters in microstrip technology,” Internal Report PhDEngScITESO-20-21-R
(CAECAS-20-09-R), ITESO, Tlaquepaque, Mexico, Sep. 2020. [223] A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and F. J. Leal-Romo,
“Optimizing a buck voltage regulator for a PDN application,” Internal Report
PhDEngScITESO-20-19-R (CAECAS-20-08-R), ITESO, Tlaquepaque, Mexico, Aug.
2020.
[211] A. Viveros-Wacher, A. Norman, and J. E. Rayas-Sánchez, “An
introduction to bit error rate extrapolation modeling,” Internal Report
PhDEngScITESO-19-18-R (CAECAS-19-14-R), ITESO, Tlaquepaque, Mexico, Nov.
2019. [210] A. E. Moreno-Mojica and J. E. Rayas-Sánchez, “A study on the resonant
frequencies of an array of decoupling capacitors for PDN applications,” Internal
Report PhDEngScITESO-19-16-R (CAECAS-19-13-R), ITESO, Tlaquepaque,
Mexico, Oct. 2019. [209] R. Loera-Díaz, J. E. Rayas-Sánchez, and Z. Brito-Brito, “A formulation
for circuit parameter extraction based on the Kullback-Leibler distance,”
Internal Report PhDEngScITESO-19-10-R (CAECAS-19-12-R), ITESO,
Tlaquepaque, Mexico, Jul. 2019. [208] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado,
“Exploring platform PDN cost reduction opportunity using PDN metamodeling
optimization,” Internal Report PhDEngScITESO-19-09-R (CAECAS-19-11-R),
ITESO, Tlaquepaque, Mexico, Jun. 2019. [207] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado,
“Finding a dual sensing voltage regulator recipe using PDN metamodeling
optimization,” Internal Report PhDEngScITESO-19-08-R (CAECAS-19-10-R),
ITESO, Tlaquepaque, Mexico, Jun. 2019. [206] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado,
“Optimization flow to enhance power delivery design by employing surrogate black
box models,” Internal Report PhDEngScITESO-19-07-R (CAECAS-19-09-R),
ITESO, Tlaquepaque, Mexico, Jun. 2019. [205] F. J. Leal-Romo, J. E. Rayas-Sánchez, A. E. Moreno-Mojica, and
J. L. Chávez-Hurtado, “A methodology for custom analysis and design of power
delivery networks based on lumped model extraction,” Internal Report
PhDEngScITESO-19-06-R (CAECAS-19-08-R), ITESO, Tlaquepaque, Mexico, Jun.
2019. [204] F. A. Velarde-González and J. E. Rayas-Sánchez, “Comparison of
modeling approaches for transistor degradation,” Internal Report
CAECAS-19-07-R, ITESO, Tlaquepaque, Mexico, Jun. 2019. [203] M. Cabrera-Gómez and J. E. Rayas-Sánchez, “Matlab driver for
parameterized full-wave EM simulations in PowerSI of microstrip circuits,”
Internal Report CAECAS-19-06-R, ITESO, Tlaquepaque, Mexico, Jun. 2019. [202] F. A. Velarde-González and J. E. Rayas-Sánchez, “Integration of aging
models into multiple EDA environments,” Internal Report CAECAS-19-05-R,
ITESO, Tlaquepaque, Mexico, May 2019. [201] A. E. Moreno-Mojica, F. J. Leal-Romo, and J. E. Rayas-Sánchez, “Power
delivery network impedance profile optimization,” Internal Report
PhDEngScITESO-19-03-R (CAECAS-19-04-R), ITESO, Tlaquepaque, Mexico, May
2019. [200] B. Mercado-Casillas and J. E. Rayas-Sánchez, “Accurate and
computationally efficient power delivery network lumped models obtained from
parameter extraction,” Internal Report
CAECAS-19-03-R, ITESO, Tlaquepaque, Mexico, Apr. 2019. [199] F. A. Velarde-González and J. E. Rayas-Sánchez, “Modelling and
simulation of aging effects in CMOS circuits,” Internal Report
CAECAS-19-02-R, ITESO, Tlaquepaque,
Mexico, Mar. 2019. [198] A. Viveros-Wacher, J. E. Rayas-Sánchez, and Z. Brito-Brito, “A
generalized formulation for neural modeling of analog faults,” Internal Report
PhDEngScITESO-19-01-R (CAECAS-19-01-R),
ITESO, Tlaquepaque, Mexico, Jan. 2019. [197] J. Dávalos-Guzmán, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“State of the art of reconfigurable high frequency filters,” Internal Report
PhDEngScITESO-18-32-R (CAECAS-18-13-R),
ITESO, Tlaquepaque, Mexico, Dec. 2018. [196] R. J. Sánchez-Mesa, D. M. Cortés-Hernández, B. Gálvez-Sahagún,
J. E. Rayas-Sánchez, and Z. Brito-Brito,
“A novel high-performance length matching element for high-speed
interconnect differential channels,” Internal Report
PhDEngScITESO-18-29-R (CAECAS-18-12-R),
ITESO, Tlaquepaque, Mexico, Nov. 2018. [195] F. J. Leal-Romo, J. L. Chávez-Hurtado and J. E. Rayas-Sánchez,
“Developing efficient surrogate based models to enhance power integrity
analyses,” Internal Report
PhDEngScITESO-18-28-R (CAECAS-18-11-R), ITESO, Tlaquepaque, Mexico, Nov.
2018. [194] R. J. Sánchez-Mesa, D. M. Cortés-Hernández, J. E.
Rayas-Sánchez, Z. Brito-Brito, and L. de-la-Mora-Hernández, “EM parametric study
of length matching elements exploiting a Matlab-Python driver for ANSYS HFSS,”
Internal Report PhDEngScITESO-18-27-R
(CAECAS-18-10-R), ITESO, Tlaquepaque, Mexico, Nov. 2018. [193] R. Loera-Díaz, J. E. Rayas-Sánchez, and Z. Brito-Brito,
“Monte-Carlo analysis, yield estimation, and worst-case prediction of a
microstrip filter,” Internal Report
PhDEngScITESO-18-23-R (CAECAS-18-09-R), ITESO, Tlaquepaque, Mexico, Aug.
2018. [192] A. Viveros-Wacher and J. E. Rayas-Sánchez, “Analog fault
identification in RF circuits using artificial neural networks and constrained
parameter extraction,” Internal Report
PhDEngScITESO-18-21-R (CAECAS-18-08-R), ITESO, Tlaquepaque, Mexico, Aug.
2018. [191] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Flexible metallic interconnect envisioned for high frequency signal transfer
amongst two printed circuit boards,” Internal Report
PhDEngScITESO-18-12-R (CAECAS-18-07-R),
ITESO, Tlaquepaque, Mexico, May 2018. [190] F. A. Velarde-González and J. E. Rayas-Sánchez, “Aging
mechanisms in CMOS technologies,” Internal Report
CAECAS-18-06-R, ITESO, Tlaquepaque,
Mexico, Apr. 2018. [189] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Assembly process and test of a module in package customized for the automotive
environment,” Internal Report
PhDEngScITESO-18-09-R (CAECAS-18-05-R), ITESO, Tlaquepaque, Mexico, Apr.
2018. [188] A. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, M. A.
Dávalos-Santana, E. A. Vega-Ochoa, and J. E. Rayas-Sánchez, “Jitter tolerance
acceleration using the golden section optimization technique,” Internal Report
PhDEngScITESO-18-07-R (CAECAS-18-04-R),
ITESO, Tlaquepaque, Mexico, Apr. 2018. [187] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “Design
of a module in package tailored for the automotive environment,” Internal Report
PhDEngScITESO-18-05-R (CAECAS-18-03-R),
ITESO, Tlaquepaque, Mexico, Apr. 2018. [186] F. E. Rangel-Patiño, J. E. Rayas-Sánchez, A. Viveros-Wacher, E.
A. Vega-Ochoa, and N. Hakim, “High-speed links receiver optimization in
post-silicon validation exploiting Broyden-based input space mapping,” Internal
Report PhDEngScITESO-18-04-R
(CAECAS-18-02-R), ITESO, Tlaquepaque, Mexico, Apr. 2018. [185] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “Solder
ball technologies for system in package and board to board solutions for the
automotive,” Internal Report
PhDEngScITESO-18-02-R (CAECAS-18-01-R), ITESO, Tlaquepaque, Mexico, Mar.
2018. [184] A. Viveros-Wacher, F. E. Rangel-Patiño, J. L. Chavez-Hurtado,
and J. E. Rayas-Sánchez, “Eye diagram system margining surrogate modeling and
optimization,” Internal Report
PhDEngScITESO-17-49-R (CAECAS-17-22-R), ITESO, Tlaquepaque, Mexico, Dec.
2017. [183] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “A
comparison between connectorless board to board interconnects for the automotive
electronics industry,” Internal Report PhDEngScITESO-17-46-R (CAECAS-17-21-R), ITESO, Tlaquepaque, Mexico,
Dec. 2017. [182] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “An
overview on board to board interconnecting technologies for the advanced
automotive industry,” Internal Report
PhDEngScITESO-17-44-R (CAECAS-17-20-R), ITESO, Tlaquepaque, Mexico, Dec.
2017. [181] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “Cost
reduction approaches for systems requiring high-speed high-density printed
circuit board interconnects,” Internal Report
PhDEngScITESO-17-41-R (CAECAS-17-19-R), ITESO, Tlaquepaque, Mexico,
Dec. 2017. [180] M. de Aguinaga-Muro and J. E. Rayas-Sánchez, “Simulations of a
microstrip line with test fixtures on Sonnet via Matlab,” Internal Report
CAECAS-17-18-R, ITESO, Tlaquepaque,
Mexico, Dec. 2017. [179] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Challenges in the connected car requirements from a hardware perspective to
enable safer and competitive next-generation driver information systems,”
Internal Report PhDEngScITESO-17-38-R
(CAECAS-17-17-R), ITESO, Tlaquepaque, Mexico, Nov. 2017. [178] F. J. Leal-Romo, J. L. Silva-Perales, C. López-Limón, and J. E.
Rayas-Sánchez, “Optimizing phase settings of high-frequency voltage regulators
for power delivery applications,” Internal Report
PhDEngScITESO-17-34-R (CAECAS-17-16-R), ITESO, Tlaquepaque, Mexico,
Nov. 2017. [177] F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and
N. Hakim, “Direct optimization of a PCI Express link equalization in industrial
post-silicon validation,” Internal Report
PhDEngScITESO-17-32-R (CAECAS-17-15-R), ITESO, Tlaquepaque, Mexico, Nov.
2017. [176] F. J. Leal-Romo and J. E. Rayas-Sánchez, “ADS-Matlab automation
driver,” Internal Report
PhDEngScITESO-17-31-R (CAECAS-17-14-R), ITESO, Tlaquepaque, Mexico, Nov.
2017. [175] F. E. Rangel-Patiño, J. E. Rayas-Sánchez, A. Viveros-Wacher, J.
L. Chávez-Hurtado, E. A. Vega-Ochoa, and N. Hakim, “Post-silicon receiver
equalization metamodeling by using artificial neural networks,” Internal Report
PhDEngScITESO-17-29-R (CAECAS-17-13-R),
ITESO, Tlaquepaque, Mexico, Aug. 2017. [174] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Circuit modeling
with artificial neural networks,” Internal Report
PhDEngScITESO-17-25-R (CAECAS-17-12-R), ITESO, Tlaquepaque, Mexico,
Jul. 2017. [173] R. J. Sánchez-Mesa, J. E. Rayas-Sánchez, and Z. Brito-Brito,
“An optimization-based method to extract equivalent lumped circuital models of
test fixtures for planar microstrip structures,” Internal Report
PhDEngScITESO-17-24-R (CAECAS-17-11-R),
ITESO, Tlaquepaque, Mexico, Jul. 2017. [172] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “Space mapping
technique exploiting linear approximations,” Internal Report
PhDEngScITESO-17-21-R (CAECAS-17-10-R),
ITESO, Tlaquepaque, Mexico, Jun. 2017. [171] M. de Aguinaga-Muro and J. E. Rayas-Sánchez, “Driving Sonnet
simulations from Matlab,” Internal Report
CAECAS-17-09-R, ITESO, Tlaquepaque, Mexico, Jun. 2017. [170] A. Viveros-Wacher and J. E. Rayas-Sánchez, “Analog fault
modeling with artificial neural networks,” Internal Report
PhDEngScITESO-17-16-R (CAECAS-17-08-R), ITESO, Tlaquepaque, Mexico,
May 2017. [169] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “A formulation
for solving linear and non-linear systems using linear approximations,” Internal
Report PhDEngScITESO-17-10-R
(CAECAS-17-07-R), ITESO, Tlaquepaque, Mexico, May 2017. [168] F. E. Rangel-Patiño, J. L. Chávez-Hurtado, A. Viveros-Wacher,
J. E. Rayas-Sánchez, and N. Hakim,
“Coarse surrogates for eye diagram system margining optimization in a server
post-silicon validation platform,” Internal Report
PhDEngScITESO-17-08-R (CAECAS-17-06-R),
ITESO, Tlaquepaque, Mexico, May 2017. [167] F. J. Leal-Romo, M. Cabrera-Gómez, D. M. García-Mora, and J. E.
Rayas-Sánchez, “Design optimization of a 3D spiral inductor using space
mapping,” Internal Report
PhDEngScITESO-17-06-R (CAECAS-17-05-R), ITESO, Tlaquepaque, Mexico, May
2017. [166] J. R. Alejos-Jiménez and J. E. Rayas-Sánchez, “Comparing the
performance of the calibrated simulated annealing against Nelder-Mead,
sequential quadratic programming, and genetic algorithms,” Internal Report
CAECAS-17-04-R, ITESO, Tlaquepaque,
Mexico, May 2017. [165] F. E. Rangel-Patiño, I. Duron-Rosales, J. E. Rayas-Sánchez, J.
L. Chávez-Hurtado, and N. Hakim, “Reconfigurable FIR filter coefficient
optimization in post-silicon validation to improve eye diagram for optical
interconnects,” Internal Report
PhDEngScITESO-17-05-R (CAECAS-17-03-R), ITESO, Tlaquepaque, Mexico, May
2017. [164] R. J. Sánchez-Mesa, J. E. Rayas-Sánchez, and Z. Brito-Brito,
“Comparison between full-wave EM simulations and experimental measurements for a
microstrip transmission line,” Internal Report
PhDEngScITESO-17-02-R (CAECAS-17-02-R), ITESO, Tlaquepaque, Mexico,
Feb. 2017. [163] A. Viveros-Wacher and J. E. Rayas-Sánchez, “A brief review of
fault diagnosis methods,” Internal Report
PhDEngScITESO-17-01-R (CAECAS-17-01-R), ITESO, Tlaquepaque, Mexico, Jan.
2017. [162] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Temperature effects in automotive-grade high speed interconnects,” Internal
Report PhDEngScITESO-16-31-R
(CAECAS-16-15-R), ITESO, Tlaquepaque, Mexico, Dec. 2016. [161] F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “A
holistic formulation for system margining and jitter tolerance optimization in
industrial post-silicon validation,” Internal Report
PhDEngScITESO-16-25-R (CAECAS-16-14-R), ITESO, Tlaquepaque, Mexico,
Dec. 2016. [160] J. R. Alejos-Jiménez and J. E. Rayas-Sánchez, “Validation of
the simulated annealing configuration methodology using a microstrip filter
design optimization problem,” Internal Report
CAECAS-16-13-R, ITESO, Tlaquepaque,
Mexico, Dec. 2016. [159] J. L. Chávez-Hurtado, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Multiphysics modeling of microwave structures in frequency domain using PSM,”
Internal Report PhDEngScITESO-16-21-R
(CAECAS-16-12-R), ITESO, Tlaquepaque, Mexico, Dec. 2016. [158] A. Viveros-Wacher and J. E. Rayas-Sánchez, “An introduction to
analog faults,” Internal Report
PhDEngScITESO-16-14-R (CAECAS-16-11-R), ITESO, Tlaquepaque, Mexico, Nov.
2016. [157] J. L. Chávez-Hurtado, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Multiphysical characterization of microwave structures in frequency domain,”
Internal Report PhDEngScITESO-16-13-R
(CAECAS-16-10-R), ITESO, Tlaquepaque, Mexico, Nov. 2016. [156] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “Design of
experiments implementation towards optimization of power distribution networks,”
Internal Report PhDEngScITESO-16-12-R
(CAECAS-16-09-R), ITESO, Tlaquepaque, Mexico, Nov. 2016. [155] O. Gallardo-García and J. E. Rayas-Sánchez, “Driving an
accurate electrical Li-Ion battery SPICE model with Scilab,” Internal Report
CAECAS-16-08-R, ITESO, Tlaquepaque,
Mexico, Sep. 2016. [154] J. A. Robledo-Mariscal and J. E. Rayas-Sánchez, “A minimax
formulation for a frequency domain numeric optimization of a non-spec-compliant
USB3 topology,” Internal Report
CAECAS-16-07-R, ITESO, Tlaquepaque, Mexico, Aug. 2016. [153] A. Viveros-Wacher and J. E. Rayas-Sánchez, “Maximizing the area
of a receiver eye diagram using central composite design,” Internal Report
PhDEngScITESO-16-09-R (CAECAS-16-06-R),
ITESO, Tlaquepaque, Mexico, Jul. 2016. [152] J. R. Alejos-Jiménez and J. E. Rayas-Sánchez, “Configuring
simulated annealing for high-frequency design optimization,” Internal Report
CAECAS-16-05-R, ITESO, Tlaquepaque,
Mexico, Jun. 2016. [151] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “An initial
temperature-dependent polynomial surrogate model of a microstrip bandpass filter
using COMSOL Multiphysics,” Internal Report
PhDEngScITESO-16-03-R (CAECAS-16-04-R), ITESO, Tlaquepaque, Mexico,
Feb. 2016. [150] J. García-Bedoy-Torres and J. E. Rayas-Sánchez, “Parallelizing
the harmonic balance algorithm in Python,” Internal Report
CAECAS-16-03-R, ITESO, Tlaquepaque, Mexico, Feb. 2016. [149] J. A. Robledo-Mariscal and J. E. Rayas-Sánchez, “Frequency
domain simulations of high speed digital interconnects and comparison with
classical time domain analysis,” Internal Report
CAECAS-16-02-R, ITESO, Tlaquepaque,
Mexico, Feb. 2016. [148] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “An overview on
channel equalization for high-speed serial links,” Internal Report
PhDEngScITESO-16-01-R (CAECAS-16-01-R), ITESO, Tlaquepaque, Mexico,
Jan. 2016. [147] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Modeling of a low-cost PCB differential interconnect using several commercially
available simulators,” Internal Report
PhDEngScITESO-15-19-R (CAECAS-15-17-R), ITESO, Tlaquepaque, Mexico, Dec.
2015. [146] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “System
marginality validation: an on-die silicon test methodology,” Internal Report
PhDEngScITESO-15-17-R (CAECAS-15-16-R),
ITESO, Tlaquepaque, Mexico, Dec. 2015. [145] J. A. Robledo-Mariscal and J. E. Rayas-Sánchez, “A minimax
formulation for a time domain numeric optimization of a non-spec-compliant USB3
topology,” Internal Report CAECAS-15-15-R,
ITESO, Tlaquepaque, Mexico, Dec. 2015. [144] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “General
formulation for polynomial-based surrogate modeling of microwave structures in
frequency domain using the multinomial theorem,” Internal Report
PhDEngScITESO-15-12-R (CAECAS-15-14-R), ITESO, Tlaquepaque, Mexico,
Nov. 2015. [143] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “Power
delivery challenges for cloud computing applications,” Internal Report
PhDEngScITESO-15-11-R (CAECAS-15-13-R),
ITESO, Tlaquepaque, Mexico, Nov. 2015. [142] J. R. Alejos-Jiménez and J. E. Rayas-Sánchez, “Basic concepts
on simulated annealing and its applications,” Internal Report
CAECAS-15-12-R, ITESO, Tlaquepaque, Mexico, Aug. 2015. [141] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “Power
conversion in power delivery networks,” Internal Report
PhDEngScITESO-15-09-R (CAECAS-15-11-R), ITESO, Tlaquepaque, Mexico,
Aug. 2015. [140] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “Polynomial
surrogate modeling based on the multinomial theorem,” Internal Report
PhDEngScITESO-15-08-R (CAECAS-15-10-R),
ITESO, Tlaquepaque, Mexico, Aug. 2015. [139] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Towards a
suitable objective function formulation for equalizer optimization for
post-silicon electrical validation,” Internal Report
PhDEngScITESO-15-06-R (CAECAS-15-09-R),
ITESO, Tlaquepaque, Mexico, Jun. 2015. [138] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “Surrogate
modeling using polynomials,” Internal Report
PhDEngScITESO-15-05-R (CAECAS-15-08-R),
ITESO, Tlaquepaque, Mexico, Jun. 2015. [137] J. A. Robledo-Mariscal and J. E. Rayas-Sánchez, “An
illustrative signal integrity simulation example of a non-spec compliant
high-speed digital interconnect,” Internal Report
CAECAS-15-07-R, ITESO, Tlaquepaque,
Mexico, Jun. 2015. [136] J. E. Gutiérrez-Morales and J. E. Rayas-Sánchez, “Analysis of
the distributed capacitance and the electromagnetic fields of a microstrip line
using COMSOL,” Internal Report
CAECAS-15-06-R, ITESO, Tlaquepaque, Mexico, May 2015. [135] J. García-Bedoy-Torres and J. E. Rayas-Sánchez, “The harmonic
balance algorithm and a Python implementation,” Internal Report
CAECAS-15-05-R, ITESO, Tlaquepaque,
Mexico, May 2015. [134] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “Power
delivery design methodologies,” Internal Report
PhDEngScITESO-15-03-R (CAECAS-15-04-R),
ITESO, Tlaquepaque, Mexico, Apr. 2015. [132] F. J. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “An
introduction to power delivery,” Internal Report
PhDEngScITESO-15-02-R (CAECAS-15-02-R),
ITESO, Tlaquepaque, Mexico, Feb. 2015. [131] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Eye-diagram
approaches and their correlation for high speed interconnects analysis,”
Internal Report PhDEngScITESO-15-01-R
(CAECAS-15-01-R), ITESO, Tlaquepaque, Mexico, Feb. 2015. [130] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Precision awareness in measurements of PCB high speed interconnects,” Internal
Report PhDEngScITESO-14-20-R
(CAECAS-14-13-R), ITESO, Tlaquepaque, Mexico, Dec. 2014. [129] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Impedance matching optimization of a low-cost PCB differential interconnect,”
Internal Report PhDEngScITESO-14-18-R
(CAECAS-14-12-R), ITESO, Tlaquepaque, Mexico, Dec. 2014. [128] J. C. Cervantes-González, J. E. Rayas-Sánchez, C. A. López, J.
L. Chávez-Hurtado, T. A. Gómez-Hernández, and Z. Brito-Brito, “EM simulations of
a T-slot PIFA considering coupling effects to handset components and human
head,” Internal Report CAECAS-14-11-R,
ITESO, Tlaquepaque, Mexico, Dec. 2014. [127] J. A. Robledo-Mariscal and J. E. Rayas-Sánchez, “An
introduction to signal integrity simulations for high-speed interconnects in
computing platforms,” Internal Report
CAECAS-14-10-R, ITESO, Tlaquepaque, Mexico, Dec. 2014. [126] M. R. Bueno-Pérez and J. E. Rayas-Sánchez, “Full-wave EM
simulation of four-cascaded CRLH unit-cells microstrip structure using Sonnet,”
Internal Report CAECAS-14-09-R, ITESO,
Tlaquepaque, Mexico, Dec. 2014. [125] F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim,
“Challenges and opportunities in post-silicon electrical validation of high
speed I/O’s,” Internal Report
PhDEngScITESO-14-08-R (CAECAS-14-08-R), ITESO, Tlaquepaque, Mexico, Oct.
2014. [124] J. L. Chávez-Hurtado, J. E. Rayas-Sánchez, and Z. Brito-Brito,
“COMSOL configuration for the EM simulation of a single-layer SIW interconnect
with transitions to microstrip lines,” Internal Report
PhDEngScITESO-14-07-R (CAECAS-14-07-R), ITESO, Tlaquepaque, Mexico,
Oct. 2014. [123] M. R. Bueno-Pérez and J. E. Rayas-Sánchez, “Full-wave EM
simulation of a CRLH unit-cell microstrip structure using Sonnet,” Internal
Report CAECAS-14-06-R, ITESO,
Tlaquepaque, Mexico, Oct. 2014. [122] J. R. del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Impedance matching analysis of a low-cost PCB differential interconnect,”
Internal Report PhDEngScITESO-14-05-R
(CAECAS-14-05-R), ITESO, Tlaquepaque, Mexico, Aug. 2014. [121] J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “Four benchmark
microstrip line models,” Internal Report
PhDEngScITESO-14-03-R (CAECAS-14-04-R), ITESO, Tlaquepaque, Mexico, Jul.
2014. [120] F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Computer-aided
design: historical review, state of the art, and future trends,” Internal Report
PhDEngScITESO-14-01-R (CAECAS-14-03-R),
ITESO, Tlaquepaque, Mexico, Jul. 2014. [118] Z. Brito-Brito, J. L. Chávez-Hurtado, and J. E. Rayas-Sánchez,
“EM model for a fifth order Chebyshev bandstop microstrip filter with L-shaped
resonators using ADS momentum,” Internal Report
CAECAS-14-01-R, ITESO, Tlaquepaque,
Mexico, Mar. 2014. [117] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “A parameter
extraction process for equivalent circuit models of a composite
right/left-handed transmission line,” Internal Report
CAECAS-13-10-R, ITESO, Tlaquepaque, Mexico, Dec. 2013. [116] G. Gómez-del-Toro, T. A.
Gómez-Hernández, J. E. Rayas-Sánchez, and Z. Brito-Brito, “Initial study of a
microstrip high-speed interconnect using Sonnet and Aplac,” Internal Report
CAECAS-13-09-R, ITESO, Tlaquepaque,
Mexico, Dec. 2013. [115] J. L. Chávez-Hurtado, Z. Brito-Brito, and J. E. Rayas-Sánchez,
“Coarse and fine models for a fifth order Chebyshev bandstop microstrip filter
with L-shaped resonators using COMSOL and Sonnet,” Internal Report
PhDEngScITESO-13-01-R (CAECAS-13-08-R),
ITESO, Tlaquepaque, Mexico, Dec. 2013. [114] T. A. Gómez-Hernández, R. Bustos-Ramírez, J. E. Rayas-Sánchez,
Z. Brito-Brito, J. C. Cervantes-González, and C. A. López, “Configuration of
coaxial ports in COMSOL for reliable electromagnetic simulations,” Internal
Report CAECAS-13-07-R, ITESO,
Tlaquepaque, Mexico, Dec. 2013. [113] J. García-Bedoy-Torres and J. E. Rayas-Sánchez, “Yield
optimization of high-frequency circuits exploiting a multi-threaded
implementation,” Internal Report
CAECAS-13-06-R, ITESO, Tlaquepaque, Mexico, Nov. 2013. [112] R. Bustos-Ramírez, T. A. Gómez-Hernández, J. C.
Cervantes-González, Z. Brito-Brito, J. E. Rayas-Sánchez and C. A. López,
“Alternative EM simulation of a package via-stripline-via interconnect using
COMSOL,” Internal Report CAECAS-13-05-R,
ITESO, Tlaquepaque, Mexico, May 2013. [111] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez, “EM-based
modeling of a through-hole via using a linear input space mapping technique,”
Internal Report CAECAS-13-04-R, ITESO,
Tlaquepaque, Mexico, Apr. 2013. [110] Z. Brito-Brito and J. E. Rayas-Sánchez, “Losses test for
geometrically symmetric and asymmetric structures simulated in COMSOL,” Internal
Report CAECAS-13-03-R, ITESO,
Tlaquepaque, Mexico, Feb. 2013. [109] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez, “Test examples
of an EM-based modeling using a linear input space mapping technique
manipulating 2, 3 and 4 input design parameters,” Internal Report
CAECAS-13-02-R, ITESO, Tlaquepaque, Mexico, Jan. 2013. [108] J. C. Martínez-Meza and J. E. Rayas-Sánchez, “Optimización
numérica de un filtro microcinta pasa-banda con líneas acopladas,” Internal
Report CAECAS-13-01-R, ITESO,
Tlaquepaque, Mexico, Jan. 2013. [107] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “Physical
implementations of composite right/left-handed transmission lines,” Internal
Report CAECAS-12-23-R, ITESO,
Tlaquepaque, Mexico, Dec. 2012. [106] J. C. Cervantes-González, C. A. López, and J. E. Rayas-Sánchez,
“EM simulation of a package via-stripline-via interconnect using COMSOL,”
Internal Report CAECAS-12-22-R, ITESO,
Tlaquepaque, Mexico, Nov. 2012. [104] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez, “EM-based
modeling of a microstrip right angle bend using a linear input space mapping
technique,” Internal Report CAECAS-12-20-R,
ITESO, Tlaquepaque, Mexico, Sep. 2012. [103] J. E. Rayas-Sánchez, J. C. Cervantes-González, C. A. López, Z.
Brito-Brito, and J. Aguilar-Torrentera, “Developing
coarse and fine EM COMSOL models of a microstrip low-pass filter for space
mapping optimization,” Internal Report
CAECAS-12-19-R, ITESO, Tlaquepaque, Mexico, Sep. 2012. [102] J. C. Cervantes-González, C. A. López, and J. E. Rayas-Sánchez,
“EM simulation of a package via using COMSOL,” Internal Report
CAECAS-12-18-R, ITESO, Tlaquepaque, Mexico, Aug. 2012. [101] J. Aguilar-Torrentera, J. C. Cervantes-González and J. E.
Rayas-Sánchez, “EM-thermo-mechanical performance analysis of a low-pass filter
based on defected ground units using COMSOL simulation,” Internal Report
CAECAS-12-17-R, ITESO, Tlaquepaque,
Mexico, Aug. 2012. [100] J. E. Rayas-Sánchez and Z. Brito-Brito, “Selecting suitable
optimization methods for direct EM optimization of low-fidelity models in
COMSOL,” Internal Report CAECAS-12-16-R,
ITESO, Tlaquepaque, Mexico, Aug. 2012. [99] J. García-Bedoy-Torres and J. E. Rayas-Sánchez,
“Massively parallel implementation of the harmonic balance algorithm – a review
of the state of the art,” Internal Report
CAECAS-12-15-R, ITESO, Tlaquepaque, Mexico, Jul. 2012. [98] J. C. Martínez-Meza and J. E. Rayas-Sánchez,
“Diseño de un filtro microcinta pasa-banda con líneas acopladas
utilizando simuladores circuitales y electromagnéticos,” Internal Report
CAECAS-12-14-R, ITESO, Tlaquepaque,
Mexico, Jul. 2012. [97] Z. Brito-Brito, J. C. Cervantes-González, J. E.
Rayas-Sánchez, and C. A. López, “EM-thermo-mechanical simulation of a microstrip
bandstop notch filter using COMSOL Multiphysics,” Internal Report
CAECAS-12-13-R, ITESO, Tlaquepaque, Mexico, Jun. 2012. [96] J. C. Cervantes-González, Z. Brito-Brito, C. A.
López, and J. E. Rayas-Sánchez, “EM-thermo-mechanical simulation of a microstrip
bandpass filter using COMSOL Multiphysics,” Internal Report
CAECAS-12-12-R, ITESO, Tlaquepaque,
Mexico, Jun. 2012. [95] J. E. Rayas-Sánchez and Z. Brito-Brito, “Optimal
configuration of lumped ports in COMSOL for non-resonant planar structures,”
Internal Report CAECAS-12-11-R, ITESO,
Tlaquepaque, Mexico, Jun. 2012. [94] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “A
parameter extraction process for equivalent circuit models of a purely
right-handed transmission line in Matlab,” Internal Report
CAECAS-12-10-R, ITESO, Tlaquepaque,
Mexico, Jun. 2012. [93] E. Estrada-Arámbula and J. E. Rayas-Sánchez, “Trace
width optimization to minimize the effects of a slit in the ground plane of a
microstrip line with reference plane isolated from simulation box,” Internal
Report CAECAS-12-09-R, ITESO,
Tlaquepaque, Mexico, May 2012. [92] J. C. Muñoz-Gaytan and J. E. Rayas-Sánchez,
“Experimental characterization of a printed F antenna with measurement
instruments,” Internal Report
CAECAS-12-08-R, ITESO, Tlaquepaque, Mexico, May 2012. [91] Z. Brito-Brito and J. E. Rayas-Sánchez, “EM
simulation of a lossless microstrip bandpass filter using COMSOL with lumped
ports,” Internal Report CAECAS-12-07-R,
ITESO, Tlaquepaque, Mexico, May 2012. [90] J. C. Cervantes-González, C. A. López, and J. E.
Rayas-Sánchez, “Electro-thermo-mechanical analysis of a microstrip at uniform
temperature using COMSOL Multiphysics simulation,” Internal Report
CAECAS-12-06-R, ITESO, Tlaquepaque,
Mexico, Mar. 2012. [89] E. Estrada-Arámbula and J. E. Rayas-Sánchez,
“Effects of a slit in the ground plane on the performance of a microstrip line
with reference plane isolated from simulation box,” Internal Report
CAECAS-12-05-R, ITESO, Tlaquepaque, Mexico, Feb. 2012. [88] D. Becerra-Pérez and J. E. Rayas-Sánchez,
“Optimization of the stub-alternated and serpentine microstrip structures to
reduce far end crosstalk,” Internal Report
CAECAS-12-04-R, ITESO, Tlaquepaque, Mexico, Feb. 2012. [87] J. Aguilar-Torrentera and J. E. Rayas-Sánchez, “EM
simulation of a low-pass filter based on a microstrip defected ground structure
using COMSOL,” Internal Report
CAECAS-12-03-R, ITESO, Tlaquepaque, Mexico, Feb. 2012. [86] Z. Brito-Brito and J. E. Rayas-Sánchez, “COMSOL
simulation of an ideal stripline using lumped ports and thick metals,” Internal
Report CAECAS-12-02-R, ITESO,
Tlaquepaque, Mexico, Jan. 2012. [85] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez,
“Modeling a composite right/left-handed transmission line in Matlab with
equivalent circuits,” Internal Report
CAECAS-12-01-R, ITESO, Tlaquepaque, Mexico, Jan. 2012. [84] N. Vargas-Chávez, J. E. Rayas-Sánchez, C. A. López,
Z. Brito-Brito, and J. Aguilar-Torrentera, “Estudio paramétrico de la
configuración térmica de una línea microcinta en COMSOL,” Internal Report
CAECAS-11-25-R, ITESO, Tlaquepaque,
Mexico, Dec. 2011. [83] J. Aguilar-Torrentera, J. E. Rayas-Sánchez, and Z.
Brito-Brito, “COMSOL validation of unilateral thermal-EM simulation of a
microstrip exposed to independent heat sources,” Internal Report
CAECAS-11-24-R, ITESO, Tlaquepaque,
Mexico, Dec. 2011. [82] J. C. Muñoz-Gaytan and J. E. Rayas-Sánchez, “A
brief introduction to microstrip printed inverted F antennas,” Internal Report
CAECAS-11-23-R, ITESO, Tlaquepaque,
Mexico, Dec. 2011. [81] Z. Brito-Brito and J. E. Rayas-Sánchez, “COMSOL
simulation of an ideal stripline using lumped ports and symmetry,” Internal
Report CAECAS-11-22-R, ITESO,
Tlaquepaque, Mexico, Dec. 2011. [80] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez,
“Modeling a purely left-handed transmission line in Matlab with equivalent
circuits,” Internal Report CAECAS-11-21-R,
ITESO, Tlaquepaque, Mexico, Nov. 2011. [79] N. Vargas-Chávez, J. E. Rayas-Sánchez, and Z.
Brito-Brito, “Simulación en COMSOL de una línea microcinta ideal sin pérdidas
con puertos concentrados y comparación con otros simuladores,” Internal Report
CAECAS-11-20-R, ITESO, Tlaquepaque, Mexico, Nov. 2011. [78] E. Estrada-Arámbula and J. E. Rayas-Sánchez, “Trace
width optimization for a microstrip line on conventional and discontinuous
reference planes,” Internal Report
CAECAS-11-19-R, ITESO, Tlaquepaque, Mexico, Oct. 2011. [77] J. Aguilar-Torrentera, J. E. Rayas-Sánchez and Z.
Brito-Brito, “Electromagnetic analysis of a stripline exposed to an external
heat source using COMSOL multiphysics simulation,” Internal Report
CAECAS-11-18-R, ITESO, Tlaquepaque,
Mexico, Oct. 2011. [76] J. E. Rayas-Sánchez and N. Vargas-Chávez, “A
general method to implement fully parameterized COMSOL simulations in batch mode
driven from Matlab,” Internal Report
CAECAS-11-17-R, ITESO, Tlaquepaque, Mexico, Oct. 2011. [75] J. E. Rayas-Sánchez and N. Vargas-Chávez, “COMSOL
simulation of an ideal microstrip line using lumped ports and symmetry,”
Internal Report CAECAS-11-16-R, ITESO,
Tlaquepaque, Mexico, Oct. 2011. [74] D. Becerra-Pérez and J. E. Rayas-Sánchez, “Far-end
crosstalk reduction through “serpentine” and “stub-alternated” microstrip
structures and their impact to near-end crosstalk, insertion loss and return
loss in the frequency domain,” Internal Report
CAECAS-11-15-R, ITESO, Tlaquepaque,
Mexico, Aug. 2011. [73] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Quasi-Newton-based direct optimization of a transition between a CBCPW and a
SIW interconnect,” Internal Report
CAECAS-11-14-R, ITESO, Tlaquepaque, Mexico, Aug. 2011. [72] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez,
“Modeling a right-handed transmission line in Matlab,” Internal Report
CAECAS-11-13-R, ITESO, Tlaquepaque, Mexico, Aug. 2011. [71] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez, “How
to drive Ansoft HFSS v12.1 from Matlab,” Internal Report
CAECAS-11-12-R, ITESO, Tlaquepaque,
Mexico, Jul. 2011. [70] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Simulación electromagnética de una línea microcinta en COMSOL,” Internal Report
CAECAS-11-11-R, ITESO, Tlaquepaque,
Mexico, Jul. 2011. [69] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“EM-based design and statistical analysis of a SIW interconnect with transitions
to microstrip lines using polynomial surrogate models,” Internal Report
CAECAS-11-10-R, ITESO, Tlaquepaque, Mexico, Jul. 2011. [68] N. Vargas-Chávez, J. E. Rayas-Sánchez and C. A.
López, “Cómo manejar COMSOL Multiphysics 4.1 desde Matlab a través de la línea
de comandos,” Internal Report
CAECAS-11-09-R, ITESO, Tlaquepaque, Mexico, Jun. 2011. [67] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Implementación en Sonnet de una línea microcinta ideal sin pérdidas como
referencia de comparación para otros simuladores electromagnéticos,” Internal
Report CAECAS-11-08-R, ITESO, Tlaquepaque, Mexico, Jun. 2011. [66] E. Estrada-Arámbula and J. E. Rayas-Sánchez,
“Effects of discontinuities in the reference plane on the performance of
microstrip lines,” Internal Report
CAECAS-11-07-R, ITESO, Tlaquepaque, Mexico, Jun. 2011. [65] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“Polynomial surrogate modeling of a SIW interconnect with microstrip
transitions,” Internal Report
CAECAS-11-06-R, ITESO, Tlaquepaque, Mexico, Jun. 2011. [64] J. Aguilar-Torrentera and J. E. Rayas-Sánchez, “A
high-precision benchmark for validation of planar EM simulation using COMSOL,”
Internal Report CAECAS-11-05-R, ITESO,
Tlaquepaque, Mexico, May 2011. [63] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“Surrogate modeling of a coarse model of a SIW with microstrip transitions using
a polynomial approximation: analyzing the impact of varying seven variables,”
Internal Report CAECAS-11-04-R, ITESO,
Tlaquepaque, Mexico, Apr. 2011. [62] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez,
“Simulation of some package discontinuities using an EM simulator and a
high-frequency circuit simulator,” Internal Report
CAECAS-11-03-R, ITESO, Tlaquepaque,
Mexico, Mar. 2011. [61] D. Becerra-Pérez and J. E. Rayas-Sánchez,
“Crosstalk analysis of two parallel microstrip lines in the frequency domain,”
Internal Report CAECAS-11-02-R, ITESO,
Tlaquepaque, Mexico, Feb. 2011. [60] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“How to drive CST Microwave Studio 2010 from Matlab,” Internal Report
CAECAS-11-01-R, ITESO, Tlaquepaque, Mexico, Jan. 2011. [59] E. R. Villa-Loustaunau and J. E. Rayas-Sánchez, “A
general introduction to metamaterials,” Internal Report
CAECAS-10-13-R, ITESO, Tlaquepaque, Mexico, Dec. 2010. [58] E. Estrada-Arámbula and J. E. Rayas-Sánchez, “PCB
manufacturing effects and their impact on high-speed interconnects,” Internal
Report CAECAS-10-12-R, ITESO,
Tlaquepaque, Mexico, Dec. 2010. [57] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Optimización del diseño de líneas microcinta con barda de vías a través de
modelos sustitutos basados en funciones polinomiales interpolantes,” Internal
Report CAECAS-10-11-R, ITESO,
Tlaquepaque, Mexico, Nov. 2010. [56] D. Becerra-Pérez and J. E. Rayas-Sánchez, “Sonnet
parameterization through a Python-based interface,” Internal Report
CAECAS-10-10-R, ITESO, Tlaquepaque,
Mexico, Oct. 2010. [55] B. Mercado-Casillas and J. E. Rayas-Sánchez,
“Methodology based on electromagnetic field solvers and circuital models for PDN
analysis,” Internal Report CAECAS-10-09-R,
ITESO, Tlaquepaque, Mexico, Sep. 2010. [54] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Simulation of a SIW interconnect with transitions to CBCPW using an enhanced
CST configuration,” Internal Report
CAECAS-10-08-R, ITESO, Tlaquepaque, Mexico, Aug. 2010. [53] B. Mercado-Casillas and J. E. Rayas-Sánchez, “An
introduction to power delivery networks for IC packages and printed circuit
boards,” Internal Report CAECAS-10-07-R,
ITESO, Tlaquepaque, Mexico, Jul. 2010. [52] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Validation of the line impedance computation method using a high-precision
benchmark,” Internal Report CAECAS-10-06-R,
ITESO, Tlaquepaque, Mexico, Jul. 2010. [51] D. Becerra-Pérez and J. E. Rayas-Sánchez, “An
overview on signal integrity effects,” Internal Report
CAECAS-10-05-R, ITESO, Tlaquepaque,
Mexico, Jul. 2010. [50] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Verificación de resultados en el uso de barda de vías para reducción de
interferencia en circuitos PCB,” Internal Report
CAECAS-10-04-R, ITESO, Tlaquepaque,
Mexico, Jun. 2010. [49] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Analysis of a conductor backed coplanar waveguide grounded by rows of vias
using CST microwave studio,” Internal Report
CAECAS-10-03-R, ITESO, Tlaquepaque,
Mexico, Apr. 2010. [48] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“Surrogate modeling of a coarse model of a SIW with microstrip transitions using
a polynomial approximation: analizing the impact of base points distributions,”
Internal Report CAECAS-10-02-R, ITESO,
Tlaquepaque, Mexico, Apr. 2010. [47] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Electromagnetic simulation of a conductor backed coplanar waveguide with
conductive lateral walls,” Internal Report
CAECAS-10-01-R, ITESO, Tlaquepaque, Mexico, Feb. 2010. [46] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez, “A
simplified sensitivity analysis of a substrate integrated waveguide (SIW) using
a coarse model,” Internal Report
CAECAS-09-11-R, ITESO, Tlaquepaque, Mexico, Dec. 2009. [45] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Simulación electromagnética de una línea CBCPW en Sonnet,” Internal Report
CAECAS-09-10-R, ITESO, Tlaquepaque, Mexico, Dec. 2009. [44] V. Gutiérrez-Ayala and J. E. Rayas-Sánchez,
“Comparison between three layer perceptrons and two layer perceptrons with
optimized nonlinearity for neural space mapping,” Internal Report
CAECAS-09-09-R, ITESO, Tlaquepaque,
Mexico, Nov. 2009. [43] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Simulación de una línea microcinta a través de Matlab para obtener la
configuración más adecuada de Sonnet,” Internal Report
CAECAS-09-08-R, ITESO, Tlaquepaque,
Mexico, Oct. 2009. [42] J. Aguilar-Torrentera and J. E. Rayas-Sánchez,
“Electromagnetic simulation of coplanar transmission lines,” Internal Report
CAECAS-09-07-R, ITESO, Tlaquepaque,
Mexico, Oct. 2009. [41] J. C. Martínez-Meza and J. E. Rayas-Sánchez,
“Diseño e implementación de un filtro microcinta pasa-bajas utilizando
simuladores circuitales y electromagnéticos,” Internal Report
CAECAS-09-06-R, ITESO, Tlaquepaque, Mexico, Sep. 2009. [40] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez, “A
high-precision benchmark for validation of planar EM simulations using CST MWS,”
Internal Report CAECAS-09-05-R, ITESO,
Tlaquepaque, Mexico, Aug. 2009. [39] N. Vargas-Chávez and J. E. Rayas-Sánchez,
“Simulación paramétrica circuital de una línea microcinta utilizando APLAC, y
verificación electromagnética con Sonnet y CST,” Internal Report
CAECAS-09-04-R, ITESO, Tlaquepaque, Mexico, Jul. 2009. [38] D. E. Cordero-Baltazar and J. E. Rayas-Sánchez,
“Introducción a la tecnología de guías de onda embebidas en substrato (SIW),”
Internal Report CAECAS-09-03-R, ITESO,
Tlaquepaque, Mexico, Jun. 2009. [37] C. A. Jacinto-Navarro and J. E. Rayas-Sánchez,
“Full-wave electromagnetic simulation of some discontinuities within BGA
packages,” Internal Report CAECAS-09-02-R,
ITESO, Tlaquepaque, Mexico, Jun. 2009. [36] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez,
“EM-based optimization of a single layer SIW with microstrip transitions using
linear output space mapping,” Internal Report
CAECAS-09-01-R, ITESO, Tlaquepaque,
Mexico, Apr. 2009. [35] J. E. Rayas-Sánchez, “Sonnet accuracy test using an
ideal stripline suspended on air,” Internal Report
CAECAS-08-06-R, ITESO, Tlaquepaque, Mexico, Sep. 2008. [34] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez,
“Verification of an EM-based design procedure of SIW interconnects with
microstrip transitions using CST,” Internal Report
CAECAS-08-05-R, ITESO, Tlaquepaque,
Mexico, Jul. 2008. [33] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez,
“Full-wave EM simulation of a classical rectangular waveguide using CST
Microwave Studio,” Internal Report
CAECAS-08-04-R, ITESO, Tlaquepaque, Mexico, Apr. 2008. [32] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez,
“EM-based optimization of a microstrip mitered bend using Matlab and CST
Microwave Studio,” Internal Report
CAECAS-08-03-R, ITESO, Tlaquepaque, Mexico, Feb. 2008. [31] L. N. Pérez-Acosta and J. E. Rayas-Sánchez, “Design
and optimization of a second order band-pass continuous time filter at 10.7
MHz,” Internal Report CAECAS-08-02-R,
ITESO, Tlaquepaque, Mexico, Feb. 2008. [30] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez, “Driving
CST Microwave Studio from Matlab,” Internal Report
CAECAS-08-01-R, ITESO, Tlaquepaque,
Mexico, Jan. 2008. [29] J. A. Jasso-Urzúa, J. E. Rayas-Sánchez and V.
Gutiérrez-Ayala, “Setting up CST Microwave Studio for accurate and reliable
simulation of microstrip circuits,” Internal Report
CAECAS-07-10-R, ITESO, Tlaquepaque,
Mexico, Nov. 2007. [28] L. N. Pérez-Acosta and J. E. Rayas-Sánchez, “A
comparison between classical methods and optimization-based methods to extract
SPICE MOSFET model level 1 parameters from model level [27] F. de J. Leal-Romo, E. Martínez-Guerrero and J. E.
Rayas-Sánchez, “Design of a Chebyshev band-pass filter at 10 MHz,” Internal
Report CAECAS-07-08-R, ITESO,
Tlaquepaque, Mexico, Aug. 2007. [26] L. N. Pérez-Acosta and J. E. Rayas-Sánchez, “A
numerical optimization procedure to obtain SPICE MOSFET model level 1 parameters
from model level [25] J. E. Rayas-Sánchez and V. Gutiérrez-Ayala,
“EM-based optimization of a transition from microstrip to substrate integrated
waveguide interconnect,” Internal Report
CAECAS-07-06-R, ITESO, Tlaquepaque, Mexico, Jun. 2007. [24] M. Trejo-Lam, V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Neuromodelado de un filtro rechaza-banda tipo microcinta de
doble protuberancia doblada en ángulo recto,” Internal Report
CAECAS-07-05-R, ITESO, Tlaquepaque, Mexico, May. 2007. [23] J. A. Jasso-Urzúa and J. E. Rayas-Sánchez, “EM
simulation of a microstrip notch filter with mitered bends using CST Microwave
Studio,” Internal Report CAECAS-07-04-R,
ITESO, Tlaquepaque, Mexico, May 2007. [22] J. E. Rayas-Sánchez and V. Gutiérrez-Ayala, “EM
simulation of a substrate integrated waveguide interconnect with microstrip
transitions using Sonnet,” Internal Report
CAECAS-07-03-R, ITESO, Tlaquepaque, Mexico, Feb. 2007. [21] M. Trejo-Lam, V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Evaluación del desempeño del algoritmo de neuromodelado de
circuitos usando un perceptron de tres capas,” Internal Report
CAECAS-07-02-R, ITESO, Tlaquepaque,
Mexico, Feb. 2007. [20] L. N. Pérez-Acosta, J. E. Rayas-Sánchez and E.
Martínez-Guerrero, “Optimal design of a classical CMOS OTA-Miller using
numerical methods and SPICE simulations,” Internal Report
CAECAS-07-01-R, ITESO, Tlaquepaque,
Mexico, Jan. 2007. [19] J. E. Rayas-Sánchez, “EM-based design of a
microstrip notch filter with mitered bends using the constrained Broyden-based
space mapping algorithm,” Internal Report
CAECAS-06-12-R, ITESO, Tlaquepaque, Mexico, Dec. 2006. [18] V. Gutiérrez-Ayala and J. E. Rayas-Sánchez, “A
neural space mapping algorithm based on two-layer perceptrons with optimizad
non-linearity,” Internal Report
CAECAS-06-11-R, ITESO, Tlaquepaque, Mexico, Dec. 2006. [17] L. N. Pérez-Acosta, J. E. Rayas-Sánchez and E.
Martinez-Guerrero, “A graphical study of basic common source amplification
stages,” Internal Report CAECAS-06-10-R,
ITESO, Tlaquepaque, Mexico, Sep. 2006. [16] L. J. Roglá, J. E. Rayas-Sánchez, V. E. Boria and
J. Carbonell, “Simulation of left-handed planar structures based on SRRs using
Sonnet and HFSS,” Internal Report
CAECAS-06-09-R, ITESO, Tlaquepaque, Mexico, Aug. 2006. [15] J. F. Enríquez-de-la-O and J. E. Rayas-Sánchez,
“Diseño óptimo de un amplificador con
retroalimentación paralelo-serie,”
Internal Report CAECAS-06-08-R, ITESO,
Tlaquepaque, Mexico, Jul. 2006. [14] J. F. Enríquez-de-la-O and J. E. Rayas-Sánchez,
“Diseño óptimo de un convertidor
reductor de C.D.-C.D.,” Internal Report
CAECAS-06-07-R, ITESO, Tlaquepaque, Mexico, Jul. 2006. [13] L. J. Roglá, J. E. Rayas-Sánchez, V. E. Boria and
J. Carbonell, “Optimization of the equivalent circuit of a
metamaterial
structure using Aplac and Matlab,” Internal Report
CAECAS-06-06-R, ITESO, Tlaquepaque,
Mexico, Jul. 2006. [12] J. F. Enríquez-de-la-O and J. E. Rayas-Sánchez,
“Diseño óptimo de un filtro con
retroalimentación múltiple de
octavo orden,”
Internal Report CAECAS-06-05-R, ITESO,
Tlaquepaque, Mexico, Jul. 2006. [11] J. F. Enríquez-de-la-O and J. E. Rayas-Sánchez,
“Diseño óptimo de un amplificador
diferencial,” Internal Report
CAECAS-06-04-R, ITESO, Tlaquepaque, Mexico, Jul. 2006. [10] J. E. Rayas-Sánchez, “Optimal design of a
shunt-series feedback amplifier: a tutorial introduction to circuit
optimization,” Internal Report
CAECAS-06-03-R, ITESO, Tlaquepaque, Mexico, Jul. 2006. [9] L. J. Roglá, J. E. Rayas-Sánchez, V. E.
Boria and J. Carbonell, “Evaluation of Sonnet and Aplac for modeling
left-handed
structures based on split
ring resonators over a coplanar
waveguide,” Internal
Report CAECAS-06-02-R, ITESO,
Tlaquepaque, Mexico, Jun. 2006. [8] M. Trejo-Lam, V. Gutiérrez-Ayala and J.
E. Rayas-Sánchez, “Implementación en Matlab de un algoritmo para neuromodelado
de circuitos utilizando perceptrones de tres capas,” Internal Report
CAECAS-06-01-R, ITESO, Tlaquepaque, Mexico, May 2006. [7] V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Diseño de circuitos de alta frecuencia usando mapeo espacial
neural con no linealidad regulada,” Internal Report
CAECAS-05-05-R, ITESO, Tlaquepaque,
Mexico, Nov. 2005. [6] M. Trejo-Lam, V. Gutiérrez-Ayala and J.
E. Rayas-Sánchez, “Implementación en Matlab de un algoritmo para neuromodelado
de funciones lineales,” Internal Report
CAECAS-05-04-R, ITESO, Tlaquepaque, Mexico, Sep. 2005. [5] V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Variación del porcentaje de desviación en la distribución de
puntos en forma de estrella para el algoritmo de diseño de circuitos
electrónicos basado en mapeo espacial neural,” Internal Report
CAECAS-05-03-R, ITESO, Tlaquepaque,
Mexico, Jul. 2005. [4] M. Trejo-Lam, V. Gutiérrez-Ayala and J.
E. Rayas-Sánchez, “Generación de datos de entrenamiento y prueba para el
neuromodelado de circuitos,” Internal Report
CAECAS-05-02-R, ITESO, Tlaquepaque,
Mexico, May 2005. [3] V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Diseño electromagnético de un filtro pasa- bajas tipo microcinta
usando mapeo espacial neural,” Internal Report
CAECAS-05-01-R, ITESO, Tlaquepaque,
Mexico, Apr. 2005. [2] J. E. Rayas-Sánchez, “Graphical
illustration of space mapping using a lumped pi-section low pass filter,”
Internal Report CAECAS-04-02-R, ITESO,
Tlaquepaque, Mexico, Dec. 2004. [1] V. Gutiérrez-Ayala and J. E.
Rayas-Sánchez, “Implementación en MATLAB del algoritmo de diseño de circuitos
electrónicos basado en mapeo espacial neural,” Internal Report
CAECAS-04-01-R, ITESO, Tlaquepaque,
Mexico, Nov. 2004.
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