Research Group on Computer-Aided Engineering of Circuits and Systems (CAECAS)

[81]     F. E. Rangel-Patiño, A. Viveros-Wacher, S. D. Rodriguez-Saenz, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and H. Shival, “PCIe Gen6 physical layer equalization tuning by using unsupervised and supervised machine learning techniques,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2023), San Jose, Costa Rica, Dec. 2023, pp. 105-108.

[80]     K. G. López-Araiza, F. E. Rangel-Patiño, J. E. Ascencio-Blancarte E. A. Vega-Ochoa, J. E. Rayas-Sánchez, and O. Longoria-Gándara, “A multi-stage CTLE design and optimization for PCI Express Gen6.0 link equalization,” in IEEE Latin American Electron Devices Conf. (LAEDC), Puebla, Mexico, Jul. 2023, pp. 1-4.

[79]     F. E. Rangel-Patiño, A. Viveros-Wacher, C. Rajyaguru, E. A. Vega-Ochoa, S. D. Rodriguez-Saenz, J. L. Silva-Cortes, H. Shival, and J. E. Rayas-Sánchezr, “PCIe Gen5 physical layer equalization tuning by using K-means clustering and Gaussian process regression modeling in industrial post-silicon validation,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. (NEMO-2023), Winnipeg, Canada, Jun. 2023, pp. 126-129.

[78]     F. E. Rangel-Patiño, A. Viveros-Wacher, C. Rajyaguru, E. A. Vega-Ochoa, S. D. Rodriguez-Saenz, J. L. Silva-Cortes, H. Shival, and J. E. Rayas-Sánchez, “Equalization tuning of the PCIe physical layer by using machine learning in industrial post-silicon validation,” in IEEE MTT-S Int. Microwave Symp. Dig., San Diego, CA, Jun. 2023, pp. 628.

[77]     J. E. Rayas-Sánchez and J. W. Bandler, “Basic space mapping: a retrospective and its application to design optimization of nonlinear RF and microwave circuits,” in European Microwave Conf. (EuMC-2022), Milan, Italy, Sep. 2022, pp. 12-15.

[76]     J. E. Rayas-Sánchez and J. W. Bandler, “System-level measurement-based design optimization by space mapping technology,” in IEEE MTT-S Int. Microwave Symp. Dig., Denver CO, Jun. 2022, pp. 118-120.

[75]     A. Pietrenko-Dabrowska, S. Koziel, J. W. Bandler, and J. E. Rayas-Sánchez, “EM-driven tolerance optimization of compact microwave components using response feature surrogates,” in IEEE MTT-S Int. Microwave Symp. Dig., Denver CO, Jun. 2022, pp. 107-110.

[74]     A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and F. J. Leal-Romo, “Optimizing a buck voltage regulator and the number of decoupling capacitors for a PDN application,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2021), Cali, Colombia, May 2021, pp. 1-4.

[73]     R. J. Ruiz-Urbina, F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and O. Longoria-Gándara, “Transmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2021), Cali, Colombia, May 2021, pp. 1-4.

[72]     A. E. Moreno-Mojica, J. E. Rayas-Sánchez, and F. J. Leal-Romo, “Power delivery network impedance profile and voltage droop optimization,” in European Microwave Conf. (EuMC-2020), Utrecht, The Netherlands, Jan. 2021, pp. 260-263.

[71]     R. Loera-Díaz and J. E. Rayas-Sánchez, “An objective function formulation for circuit parameter extraction based on the Kullback-Leibler distance,” in IEEE MTT-S Int. Microwave Symp. Dig., Los Angeles, CA, Aug. 2020, pp. 80-82.

[70]     J. E. Rayas-Sánchez, F. E. Rangel-Patiño, B. Mercado-Casillas, F. Leal-Romo, and J. L. Chávez-Hurtado, “Machine learning techniques and space mapping approaches to enhance signal and power integrity in high-speed links and power delivery networks,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2020), San Jose, Costa Rica, Feb. 2020, pp. 1-4.

[69]     B. Mercado-Casillas and J. E. Rayas-Sánchez, “Towards signal-power integrity analysis by efficient power delivery network lumped models obtained from parameter extraction,” in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2019), Montreal, Canada, Oct. 2019, pp. 1-3.

[68]     J. E. Rayas-Sánchez and Z. Brito-Brito, “Applications of Broyden-based input space mapping to modeling and design optimization in high-tech companies in Mexico,” in European Microwave Conf. (EuMC-2019), Paris, France, Oct. 2019, pp. 272-275.

[67]     R. J. Sánchez-Mesa, D. M. Cortés-Hernández, J. E. Rayas-Sánchez, Z. Brito-Brito, and L. de-la-Mora-Hernández, “EM parametric study of length matching elements exploiting an ANSYS HFSS Matlab-Python driver,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3.

[66]     F. Leal-Romo, J. L. Chávez-Hurtado, and J. E. Rayas-Sánchez, “Selecting surrogate-based modeling techniques for power integrity analysis,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3.

[65]     R. J. Sánchez-Mesa, D. M. Cortés-Hernández, B. Gálvez-Sahagún, J. E. Rayas-Sánchez, and Z. Brito-Brito, “A novel high-performance length matching element for high-speed interconnect differential channels,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2018), Arequipa, Peru, Dec. 2018, pp. 1-3.

[64]     F. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10.

[63]     J. E. Rayas-Sánchez, F. E. Rangel-Patiño, A. Viveros-Wacher, J. L. Chávez-Hurtado, J. R. del-Rey, F. Leal-Romo, and Z. Brito-Brito, “Industry-oriented research projects on computer-aided design of high-frequency circuits and systems at ITESO Mexico,” in European Microwave Conf. (EuMC-2018), Madrid, Spain, Sep. 2018, pp. 588-591.

[62]     A. Viveros-Wacher and J. E. Rayas-Sánchez, “Analog fault identification in RF circuits using artificial neural networks and constrained parameter extraction,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. (NEMO-2018), Reykjavik, Iceland, Aug. 2018, pp. 1-3.

[61]     F. E. Rangel-Patiño, J. E. Rayas-Sánchez, A. Viveros-Wacher, E. A. Vega-Ochoa, and N. Hakim, “High-speed links receiver optimization in post-silicon validation exploiting Broyden-based input space mapping,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. (NEMO-2018), Reykjavik, Iceland, Aug. 2018, pp. 1-3.

[60]     F. Leal-Romo, J. L. Silva-Perales, C. López-Limón, and J. E. Rayas-Sánchez, “Optimizing phase settings of high-frequency voltage regulators for power delivery applications,” in IEEE Workshop on Signal and Power Integrity (SPI-2018), Brest France, May 2018, pp. 1-4.

[59]     F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, and N. Hakim, “Direct optimization of a PCI Express link equalization in industrial post-silicon validation,” in IEEE Latin American Test Symp.  (LATS 2018), Sao Paulo, Brazil, Mar. 2018, pp. 1-6.

[58]     A. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, M. A. Dávalos-Santana, E. A. Vega-Ochoa, and J. E. Rayas-Sánchez, “Jitter tolerance acceleration using the golden section optimization technique,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2018), Puerto Vallarta, Mexico, Feb. 2018, pp. 1-4.

[57]     F. Leal-Romo, M. Cabrera-Gómez, J. E. Rayas-Sánchez, and D. M. García-Mora, “Design optimization of a planar spiral inductor using space mapping,” in Int. Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2017), San Jose, CA, Oct. 2017, pp. 1-3.

[56]     F. Rangel-Patino, J. L. Chávez-Hurtado, A. Viveros-Wacher, J. E. Rayas-Sánchez, and N. Hakim, “Eye diagram system margining surrogate-based optimization in a server silicon validation platform,” in European Microwave Conf. (EuMC-2017), Nuremberg, Germany, Oct. 2017, pp. 540-543.

[55]     J. E. Rayas-Sánchez and Z. Brito-Brito, “Academic and industrial research activities on RF and microwaves in Latin America: an overview,” in European Microwave Conf. (EuMC-2017), Nuremberg, Germany, Oct. 2017, pp. 536-539.

[54]     A. Corres-Matamoros, E. Martínez-Guerrero, and J. E. Rayas-Sánchez, “Design and validation of a portable radio-frequency diathermy prototype,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 93-96.

[53]     I. Duron-Rosales, F. Rangel-Patino, J. E. Rayas-Sánchez, J. L. Chávez-Hurtado, and N. Hakim, “Reconfigurable FIR filter coefficient optimization in post-silicon validation to improve eye diagram for optical interconnects,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 85-88.

[52]     A. Corres-Matamoros, E. Martínez-Guerrero, and J. E. Rayas-Sánchez, “A programmable CMOS voltage controlled ring oscillator for radio-frequency diathermy on-chip circuit,” in Int. Caribbean Conf. Devices, Circuits, and Systems (ICCDCS-2017), Cozumel, Mexico, Jun. 2017, pp. 65-68.

[51]     J. E. Rayas-Sánchez, “A historical account and technical reassessment of the Broyden-based input space mapping optimization algorithm,” in IEEE MTT-S Int. Microwave Symp. Dig., Honolulu, HI, Jun. 2017, pp. 1-3.

[50]     I. Lomelí-Illescas, S. A. Solis-Bustos, and J. E. Rayas-Sánchez, “Analysis of the implications of stacked devices in nano-scale technologies for analog applications,” in IEEE Latin American Test Symp. (LATS-2017), Bogota, Colombia, Mar. 2017, pp. 1-4.

[49]     F. Leal-Romo, J. E. Rayas-Sánchez, and J. He, “Design of experiments implementation towards optimization of power distribution networks,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2017), Bariloche, Argentina, Feb. 2017, pp. 1-4.

[48]     A. Viveros-Wacher and J. E. Rayas-Sánchez, “Eye diagram optimization based on design of experiments (DoE) to accelerate industrial testing of high speed links,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-3.

[47]     F. Rangel-Patino, A. Viveros-Wacher, J. E. Rayas-Sánchez, E. A. Vega-Ochoa, I. Duron-Rosales, and N. Hakim, “A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4.

[46]     J. R. del-Rey, Z. Brito-Brito, J. E. Rayas-Sánchez, and N. Izquierdo, “Temperature effects in automotive-grade high speed interconnects,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4.

[45]     J. L. Chávez-Hurtado, J. E. Rayas-Sánchez, and Z. Brito-Brito, “Multiphysics polynomial-based surrogate modeling of microwave structures in frequency domain,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-3.

[44]     I. Lomelí-Illescas, S. A. Solis-Bustos, V. H. Martínez-Sánchez and J. E. Rayas-Sánchez, “Synthesis tool for automatic layout generation of analog structures,” in IEEE ANDESCON Proc., Arequipa, Peru, Oct. 2016, pp. 1-4.

[43]     J. L. Chávez-Hurtado and J. E. Rayas-Sánchez, “Polynomial-based surrogate modeling of microwave structures in frequency domain exploiting the multinomial theorem,” in IEEE MTT-S Int. Microwave Symp. Dig., San Francisco, CA, May 2016, pp. 1-3.

[42]     J. E. Rayas-Sánchez, J. L. Chávez-Hurtado, and Z. Brito-Brito, “Enhanced formulation for polynomial-based surrogate modeling of microwave structures in frequency domain,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. RF, Microw., Terahertz App. (NEMO-2015), Ottawa, ON, Aug. 2015, pp. 1-3.

[41]     Z. Brito-Brito, J. E. Rayas-Sánchez, and J. L. Chávez-Hurtado, “Enhanced procedure to setup the simulation bounding box and the meshing scheme of a 3D finite element EM simulator for planar microwave structures,” in IEEE MTT-S Int. Microwave Symp. Dig., Phoenix, AZ, May. 2015, pp. 1-3.

[40]     J. Rafael del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect,” in IEEE Latin American Test Symp. (LATS-2015), Puerto Vallarta, Mexico, Mar. 2015, pp. 1-5.

[39]     J. L. Chávez-Hurtado, J. E. Rayas-Sánchez, and Z. Brito-Brito, “Reliable full-wave EM simulation of a single-layer SIW interconnect with transitions to microstrip lines,” in COMSOL Conf., Boston, MA, Oct. 2014, pp. 1-5..

[38]     L. M. Aguilar-Lobo, A. Garcia-Osorio, J. R. Loo-Yau, S. Ortega-Cisneros, P. Moreno, J. E. Rayas-Sánchez, and J. A. Reynoso-Hernández, “A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers,” in IEEE Int. Midwest Symp. Circuits Syst., College Station, TX, Aug. 2014, pp. 717-720.

[37]     J. E. Rayas-Sánchez and Z. Brito-Brito, “Research activities on computer-aided modeling, design and optimization of RF and microwave circuits at ITESO Mexico” in IEEE MTT-S Int. Microwave Symp. Dig., Tampa, FL, Jun. 2014, pp. 1-3.

[36]     Z. Brito-Brito, J. E. Rayas-Sánchez, J. C. Cervantes-González, and C. A. López, “Impact of 3D EM model configuration on the direct optimization of microstrip structures,” in COMSOL Conf., Boston, MA, Oct. 2013, pp. 1-5.

[35]     J. C. Cervantes-González, C. A. López, J. E. Rayas-Sánchez, Z. Brito-Brito and G. Hernández-Sosa, “Return-loss minimization of package interconnects through input space mapping using FEM-based models,” in Proc. SBMO/IEEE MTT-S Int. Microwave Optoelectronics Conf. (IMOC-2013), Rio de Janeiro, Brazil, Aug. 2013, pp. 1-4.

[34]     J. E. Rayas-Sánchez, Z. Brito-Brito, J. C. Cervantes-González, and C. A. López, “Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2012), Cuzco, Peru, Feb. 2013, pp. 1-4.

[33]     D. Becerra-Pérez and J. E. Rayas-Sánchez, “Optimization of the stub-alternated and serpentine microstrip structures to minimize far-end crosstalk,” in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS 2012), Tempe, AZ, Oct. 2012, pp. 109-112.

[32]     J. E. Rayas-Sánchez, J. Aguilar-Torrentera, Z. Brito-Brito, J. C. Cervantes-González, and C. A. López, “EM simulation of a low-pass filter based on a microstrip defected ground structure,” in COMSOL Conf., Boston, MA, Oct. 2012, pp. 1-6.

[31]     J. E. Rayas-Sánchez and E. Estrada-Arámbula, “EM-based design optimization of microstrip lines traversing a rectangular gap in the reference plane,” in Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012, pp. 197-200.

[30]     J. E. Rayas-Sánchez and Q. J. Zhang, “On knowledge-based neural networks and neuro-space mapping,” in IEEE MTT-S Int. Microwave Symp. Dig., Montreal, Canada, Jun. 2012, pp. 1-3.

[29]     F. Leal-Romo, R. Moreyra-González, and J. E. Rayas-Sánchez, “HFSS automated driver based on non-GUI scripting for EM-based design of high-frequency circuits,” in IEEE Latin American Symposium on Circuits and Systems (LASCAS 2012), Playa del Carmen, Mexico, Feb. 2012, pp. 1-4.

[28]     J. E. Rayas-Sánchez and N. Vargas-Chávez, “A linear regression inverse space mapping algorithm for EM-based design optimization of microwave circuits,” in IEEE MTT-S Int. Microwave Symp. Dig., Baltimore, MD, Jun. 2011, pp. 1-4.

[27]     J. E. Rayas-Sánchez, “EM-based design optimization of RF and microwave circuits using functional surrogate models,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Baltimore, MD, Jun. 2011.

[26]     D. Becerra-Pérez and J. E. Rayas-Sánchez, “Driving Sonnet through a Python-based interface,” in Int. Review of Progress in Applied Computational Electromagnetics (ACES 2011), Williamsburg, VA, Mar. 2011, pp. 412-417.

[25]     J. E. Rayas-Sánchez and N. Vargas-Chávez, “Design optimization of microstrip lines with via fences through surrogate modeling based on polynomial functional interpolants,” in IEEE Conf. Electrical Performance of Electronic Packaging and Systems (EPEPS-2010), Austin, TX, Oct. 2010, pp. 125-128.

[24]     J. E. Rayas-Sánchez and D. E. Cordero-Baltazar, “Impact of base points distributions on the polynomial surrogate modeling of a substrate integrated waveguide with microstrip transitions,” in Electronics, Robotics and Automotive Mechanics Conf. (CERMA 2010), Cuernavaca, Mexico, Sep. 2010, pp. 705-710.

[23]     J. E. Rayas-Sánchez, J. Aguilar-Torrentera and J. A. Jasso-Urzúa, “Surrogate modeling of microwave circuits using polynomial functional interpolants,” in IEEE MTT-S Int. Microwave Symp. Dig., Anaheim, CA, May 2010, pp. 197-200.

[22]     S. Ogurtsov, S. Koziel and J. E. Rayas-Sánchez, “Design optimization of a broadband microstrip-to-SIW transition using surrogate modeling and adaptive design specifications,” in Int. Review of Progress in Applied Computational Electromagnetics (ACES 2010), Tampere, Finland, Apr. 2010, pp. 878-883.

[21]     L. N. Pérez-Acosta and J. E. Rayas-Sánchez, “Design of a CMOS second order band-pass continuous time filter using numerical optimization,” in IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS 2009), Cancun, Mexico, Aug. 2009, pp. 204-207.

[20]     J. L. Chávez-Hurtado, E. Martínez-Guerrero and J. E. Rayas-Sánchez, “Design of reusable CMOS OTAs using CAD tools,” in IEEE Int. Midwest Symp. Circuits and Systems (MWSCAS 2009), Cancun, Mexico, Aug. 2009, pp. 228-231.

[19]     J. E. Rayas-Sánchez, “Neural space mapping approaches to EM-based statistical analysis,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Boston, MA, Jun. 2009.

[18]     J. E. Rayas-Sánchez and J. A. Jasso-Urzúa, “EM-based optimization of a single layer SIW with microstrip transitions using linear output space mapping,” in IEEE MTT-S Int. Microwave Symp. Dig., Boston, MA, Jun. 2009, pp. 525-528.

[17]     J. E. Rayas-Sánchez, “An improved EM-based design procedure for single-layer substrate integrated waveguide interconnects with microstrip transitions,” in IEEE MTT-S Int. Microwave Workshop Series in Region 9 (IMWS2009-R9) on Signal Integrity and High-Speed Interconnects, Guadalajara, Mexico, Feb. 2009, pp. 27-30.

[16]     J. E. Rayas-Sánchez and V. Gutiérrez-Ayala, “A general EM-based design procedure for single-layer substrate integrated waveguide interconnects with microstrip transitions,” in IEEE MTT-S Int. Microwave Symp. Dig., Atlanta, GA, Jun. 2008, pp. 983-986.

[15]     Q. J. Zhang and J. E. Rayas-Sánchez, “Fast parametric models for EM design using neural networks and space mapping,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Atlanta, GA, Jun. 2008.

[14]     L. N. Pérez-Acosta and J. E. Rayas-Sánchez, “A numerical optimization procedure to obtain SPICE MOSFET model level 1 parameters from model level 49,” in XIV International Workshop Iberchip (IWS2008), Puebla, Mexico, Feb. 2008, ISBN-13 978-968-7938-03-5.

[13]     J. E. Rayas-Sánchez and V. Gutiérrez-Ayala, “EM-based parametric optimization of a transition from microstrip to substrate integrated waveguide interconnect,” in 9^th IEEE Latin-American Test Workshop (LATW2008), Puebla, Mexico, Feb. 2008, pp. 145-150.

[12]     L. J. Roglá, J. E. Rayas-Sánchez, V. E. Boria and J. Carbonell, “EM-based space mapping optimization of left-handed coplanar waveguide filters with split ring resonators,” in IEEE MTT-S Int. Microwave Symp. Dig., Honolulu, HI, Jun. 2007, pp. 111-114.

[11]     L. N. Pérez-Acosta, J. E. Rayas-Sánchez and E. Martínez-Guerrero, “Optimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulations,” in XIII International Workshop Iberchip (IWS2007), Lima, Peru, Mar. 2007, pp. 387-390.

[10]     V. Gutiérrez-Ayala and J. E. Rayas-Sánchez, “High-frequency circuit design using a neural space-mapping algorithm based on a two-layer perceptron with optimized nonlinearity,” in Int. Conf. on Electronic Design Proc. (ICED2006), Veracruz, Mexico, Nov. 2006, pp. 90-95.

[9]       J. E. Rayas-Sánchez, “Linear-input and neural-output space mapping for highly accurate statistical analysis and yield prediction,” in Second Int. Workshop on Surrogate Modeling and Space Mapping for Engineering Optimization (SMSMEO-06), Lyngby, Denmark, Nov. 2006.

[8]       J. E. Rayas-Sánchez and V. Gutiérrez-Ayala, “EM-based statistical analysis and yield estimation using linear-input and neural-output space mapping,” in IEEE MTT-S Int. Microwave Symp. Dig., San Francisco, CA, June 2006, pp. 1597-1600.

[7]       V. Gutiérrez-Ayala and J. E. Rayas-Sánchez, “Diseño de circuitos de alta frecuencia usando mapeo espacial neural con no-linealidad regulada,” in XII International Workshop Iberchip (IWS2006), San José, Costa Rica, March 2006, pp. 150-153.

[6]       Q. J. Zhang, L. Zhang and J. E. Rayas-Sánchez, “Automated modeling and neuro space mapping for microwave design,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Long Beach, CA, June 2005.

[5]       J. E. Rayas-Sánchez, “Electromagnetics-based design through inverse space mapping techniques,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Fort Worth, TX, June 2004.

[4]       J. E. Rayas-Sánchez, F. Lara-Rojo and E. Martínez-Guerrero, “A linear inverse space mapping algorithm for microwave design in the frequency and transient domains,” in IEEE MTT-S Int. Microwave Symp. Dig., Fort Worth, TX, June 2004, pp. 1847-1859.

[3]       J. E. Rayas-Sánchez and J. W. Bandler, “Yield optimization of microwave circuits using neural space mapping methods,” in 3rd Annual McMaster Optimization Conference: Theory and Applications (MOPTA 03), Hamilton, ON, July 2003.

[2]       J. E. Rayas-Sánchez, “EM-based optimization of microwave circuits using artificial neural networks,” in IEEE MTT-S Int. Microwave Symp. Workshop Notes and Short Courses, Philadelphia, PA, June 2003.

[1]       J. E. Rayas-Sánchez, “A frequency-domain approach to interconnect crosstalk simulation and minimization,” in IX International Workshop Iberchip (IWS2003), Habana, Cuba, March, 2003.